參數(shù)資料
型號(hào)： AD9640-80EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 21/52頁(yè)
文件大小： 0K
描述： ADC 14BIT 80MSPS DUAL 64-LFCSP
設(shè)計(jì)資源： Interfacing ADL5534 to AD9640 High Speed ADC (CN0049)
AD9640 Eval Brd Family Gerber Files
AD9640 Eval Brd BOM
AD9640 Eval Brd Schematic
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 2
位數(shù)： 14
采樣率（每秒）： 80M
數(shù)據(jù)接口： 串行
輸入范圍： 2 Vpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 550mW @ 80MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9640
已供物品： 板
AD9640
Rev. B | Page 28 of 52
2.5
–2.5
–40
0
654
7-
0
99
TEMPERATURE (°C)
RE
F
E
R
E
NCE
V
O
L
T
AG
E
R
RO
R
(
m
V
)
2.0
1.5
1.0
0
–0.5
–1.0
–1.5
–2.0
–20
0
2040
6080
Figure 54. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
6 kΩ load (see Figure 15). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1 V.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9640 sample clock inputs
CLK+, and CLK should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK pins
via a transformer or capacitors. These pins are biased internally
(see Figure 55) and require no external bias.
0
65
47-
0
34
1.2V
AVDD
2pF
CLK–
CLK+
Figure 55. Equivalent Clock Input Circuit
Clock Input Options
The AD9640 has a very flexible clock input structure. Clock input
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of
the type of signal being used, the jitter of the clock source is of the
most concern, as described in the Jitter Considerations section.
Figure 56 and Figure 57 show two preferred methods for clocking
the AD9640 (at clock rates to 625 MHz). A low jitter clock source
is converted from a single-ended signal to a differential signal
using either an RF balun or an RF transformer. The RF balun
configuration is recommended for clock frequencies between
125 MHz and 625 MHz, and the RF transformer is recommended
for clock frequencies from 10 MHz to 200MHz. The back-to-back
Schottky diodes across the transformer/balun secondary limit
clock excursions into the AD9640 to approximately 0.8 V p-p
differential.
This helps prevent the large voltage swings of the clock from
feeding through to other portions of the AD9640, while preserving
the fast rise and fall times of the signal that are critical to a low
jitter performance.
0.1F
SCHOTTKY
DIODES:
HSMS2822
CLOCK
INPUT
50
100
CLK–
CLK+
ADC
AD9640
MINI-CIRCUITS
ADT1–1WT, 1:1Z
XFMR
06
54
7-
0
3
5
Figure 56. Transformer Coupled Differential Clock (Up to 200 MHz)
0.1F
1nF
CLOCK
INPUT
1nF
50
CLK–
CLK+
ADC
AD9640
0
6
547
-10
1
SCHOTTKY
DIODES:
HSMS2822
Figure 57. Balun Coupled Differential Clock (Up to 625 MHz)
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 58. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516 clock drivers offer excellent
jitter performance.
100
0.1F
240
240
PECL DRIVER
50k
50k
CLK–
CLK+
ADC
AD9640
CLOCK
INPUT
CLOCK
INPUT
06
547
-0
36
AD951x
Figure 58. Differential PECL Sample Clock (Up to 625 MHz)
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 59. The AD9510/
drivers offer excellent jitter performance.
100
0.1F
50k
50k
CLK–
CLK+
ADC
AD9640
CLOCK
INPUT
CLOCK
INPUT
06
547
-0
37
AD951x
LVDS DRIVER
Figure 59. Differential LVDS Sample Clock (Up to 625 MHz)
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended CMOS signal. In such applica-
tions, CLK+ should be directly driven from a CMOS gate, and
the CLK pin should be bypassed to ground with a 0.1 μF
capacitor in parallel with a 39 kΩ resistor (see Figure 60).
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