參數(shù)資料
型號(hào)： AD9709ASTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/32頁(yè)
文件大小： 0K
描述： IC DAC 8BIT DUAL 125MSPS 48-LQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1
系列： TxDAC+®
設(shè)置時(shí)間： 35ns
位數(shù)： 8
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 450mW
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤(pán)
輸出數(shù)目和類(lèi)型： 4 電流，單極；4 電流，雙極
采樣率（每秒）： 125M
產(chǎn)品目錄頁(yè)面： 785 (CN2011-ZH PDF)
配用： AD9709-EBZ-ND - BOARD EVAL FOR AD9709
AD9709
Rev. B | Page 20 of 32
SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT
Figure 39 shows the AD9709 configured to provide a unipolar
output range of approximately 0 V to 0.5 V for a doubly terminated
50 Ω cable, because the nominal full-scale current, IOUTFS, of 20 mA
flows through the equivalent RLOAD of 25 Ω. In this case, RLOAD
represents the equivalent load resistance seen by IOUTA or IOUTB.
The unused output (IOUTA or IOUTB) can be connected directly to
ACOM or via a matching RLOAD. Different values of IOUTFS and
RLOAD can be selected as long as the positive compliance range is
adhered to. One additional consideration in this mode is the
INL (see the Analog Outputs section). For optimum INL
performance, the single-ended, buffered voltage output
configuration is suggested.
AD9709
50
25
50
VOUTA = 0V TO 0.5V
IOUTFS = 20mA
IOUTA
IOUTB
00
606
-03
8
Figure 39. 0 V to 0.5 V Unbuffered Voltage Output
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 40 shows a buffered single-ended output configuration
in which the U1 op amp performs an I-V conversion on the
AD9709 output current. U1 maintains IOUTA (or IOUTB) at a
virtual ground, thus minimizing the nonlinear output
impedance effect on the INL performance of the DAC, as
discussed in the Analog Outputs section. Although this single-
ended configuration typically provides the best dc linearity
performance, its ac distortion performance at higher DAC
update rates may be limited by the slewing capabilities of U1.
U1 provides a negative unipolar output voltage, and its full-
scale output voltage is simply the product of RFB and IOUTFS. The
full-scale output should be set within U1’s voltage output swing
capabilities by scaling IOUTFS and/or RFB. An improvement in ac
distortion performance may result with a reduced IOUTFS because
the signal current U1 has to sink will be subsequently reduced.
AD9709
IOUTFS = 10mA
U1
IOUTA
IOUTB
VOUT = IOUTFS × RFB
COPT
200
RFB
200
00
60
6-
0
39
Figure 40. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS
Power Supply Rejection
Many applications seek high speed and high performance under
less than ideal operating conditions. In these applications, the
implementation and construction of the printed circuit board is
as important as the circuit design. Proper RF techniques must
be used for device selection, placement, and routing as well as
power supply bypassing and grounding to ensure optimum
performance. Figure 52 and Figure 53 illustrate the recommended
circuit board layout, including ground, power, and signal
input/output.
One factor that can measurably affect system performance is
the ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the power supply rejection ratio (PSRR).
For dc variations of the power supply, the resulting performance
of the DAC directly corresponds to a gain error associated with
the DAC’s full-scale current, IOUTFS. AC noise on the dc supplies
is common in applications where the power distribution is
generated by a switching power supply. Typically, switching
power supply noise occurs over the spectrum from tens of
kilohertz to several megahertz. The PSRR vs. frequency of the
AD9709 AVDD supply over this frequency range is shown in
90
70
85
80
75
P
S
RR
(
d
B)
0.20.3
0.40.50.60.70.80.91.01.1
FREQUENCY (MHz)
00
60
6-
0
40
Figure 41. AVDD Power Supply Rejection Ratio vs. Frequency
Note that the data in Figure 41 is given in terms of current out
vs. voltage in. Noise on the analog power supply has the effect
of modulating the internal current sources and therefore the
output current. The voltage noise on AVDD, therefore, is added
in a nonlinear manner to the desired IOUT. PSRR is very code
dependent, thus producing mixing effects that can modulate
low frequency power supply noise to higher frequencies. Worst-
case PSRR for either one of the differential DAC outputs occurs
when the full-scale current is directed toward that output. As a
result, the PSRR measurement in Figure 41 represents a worst-
case condition in which the digital inputs remain static and the
full-scale output current of 20 mA is directed to the DAC
output being measured.
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AD9709ASTZKL1 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
AD9709ASTZRL 功能描述:IC DAC 8BIT DUAL 125MSPS 48LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色產(chǎn)品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 標(biāo)準(zhǔn)包裝:91 系列:- 設(shè)置時(shí)間:4µs 位數(shù):10 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:8 電壓電源:單電源 功率耗散（最大）:2.7mW 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:14-WFDFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:14-DFN-EP（4x3） 包裝:管件 輸出數(shù)目和類(lèi)型:8 電壓，單極 采樣率（每秒）:*
AD9709ASTZRL1 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:8-Bit, 125 MSPS, Dual TxDAC Digital-to-Analog Converter
AD9709-EB 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述:
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