參數(shù)資料
型號(hào)： AD9714BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 6/80頁
文件大?。?/td> 0K
描述： IC DAC DUAL 8BIT LO PWR 40LFCSP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1
系列： TxDAC®
位數(shù)： 8
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 86mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP-VQ（6x6）
包裝： 托盤
輸出數(shù)目和類型： 4 電流，單極
采樣率（每秒）： 125M
產(chǎn)品目錄頁面： 785 (CN2011-ZH PDF)
AD9714/AD9715/AD9716/AD9717
Rev. A | Page 14 of 80
07
26
5-
00
3
PIN 1
INDICATOR
1
DB9
2
DB8
3
DB7
4
DB6
5
DVDDIO
6
DVSS
7
DVDD
8
DB5
9
DB4
10
DB3
23 QOUTP
24 RLQP
25 AVSS
26 AVDD
27 RLIP
28 IOUTP
29 IOUTN
30 RLIN
22 QOUTN
21 RLQN
11
D
B
2
12
D
B
1
13
D
B
0
(L
S
B
)
15
N
C
17
C
V
D
16
D
C
L
K
IO
18
C
L
K
IN
19
C
V
S
20
C
M
L
Q
14
N
C
33
F
S
A
D
JI
/A
U
X
I
34
R
E
F
IO
35
R
E
S
E
T
/P
IN
M
D
36
S
C
L
K
/C
L
K
M
D
37
S
D
IO
/F
O
R
M
A
T
38
39
D
B
11
(M
S
B
)
40
D
B
10
32
F
S
A
D
JQ
/A
U
X
Q
31
C
M
L
I
TOP VIEW
(Not to Scale)
AD9716
NOTES
1. NC = NO CONNECT
2. THE EXPOSED PAD IS CONNECTED TO AVSS AND
SHOULD BE SOLDERED TO THE GROUND PLANE.
EXPOSED METAL AT PACKAGE CORNERS IS
CONNECTED TO THIS PAD.
C
S
/P
W
R
D
N
Figure 4. AD9716 Pin Configuration
Table 9. AD9716 Pin Function Descriptions
Pin No.
Mnemonic
Description
1 to 4
DB[9:6]
Digital Inputs.
5
DVDDIO
Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal).
6
DVSS
Digital Common.
7
DVDD
Digital Core Supply Voltage (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD with a
1.0 μF capacitor; however, do not otherwise connect it. The LDO should not drive external loads.
8 to 12
DB[5:1]
Digital Inputs.
13
DB0 (LSB)
Digital Input (LSB).
14, 15
NC
No Connect. These pins are not connected to the chip.
16
DCLKIO
Data Input/Output Clock. Clock used to qualify input data.
17
CVDD
Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
18
CLKIN
LVCMOS Sampling Clock Input.
19
CVSS
Sampling Clock Supply Voltage Common.
20
CMLQ
Q DAC Output Common-Mode Level. When the internal on chip (QRCML) is enabled, this pin is connected to
the on-chip QRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip
(QRCML) is disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a
resistor (see the Using the Internal Termination Resistors section). The recommended value for this external
resistor is 0 Ω.
21
RLQN
Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTN externally.
22
QOUTN
Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
23
QOUTP
Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
24
RLQP
Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTP externally.
25
AVSS
Analog Common.
26
AVDD
Analog Supply Voltage (1.8 V to 3.3 V).
27
RLIP
Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTP externally.
28
IOUTP
I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
29
IOUTN
Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
30
RLIN
Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTN externally.
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