參數(shù)資料
型號： AD9715-DPG2-EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 30/80頁
文件大小： 0K
描述： ADC 12BIT DUAL 40LFCSP
標(biāo)準(zhǔn)包裝： 1
系列： TxDAC®
DAC 的數(shù)量： 2
位數(shù)： 10
采樣率（每秒）： 125M
數(shù)據(jù)接口： 串行
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： 板
已用 IC / 零件： AD9715
AD9714/AD9715/AD9716/AD9717
Rev. A | Page 36 of 80
SPI REGISTER DESCRIPTIONS
Reading these registers returns previously written values for all defined register bits, unless otherwise noted.
Table 14.
Register
Address
Bit
Name
Description
SPI Control
0x00
6
LSBFIRST
0 (default): MSB first, per SPI standard.
1: LSB first, per SPI standard.
Note that the user must always change the LSB/MSB order in single-byte
instructions to avoid erratic behavior due to bit order errors.
5
Reset
Execute software reset of SPI and controllers, reload default register values except
Register 0x00.
1: sets software reset; write 0 on the next (or any following) cycle to release reset.
4
LNGINS
0 (default): the SPI instruction word uses a 5-bit address.
1: the SPI instruction word uses a 13-bit address.
Power-Down
0x01
7
LDOOFF
0 (default): LDO voltage regulator on.
1: turns core LDO voltage regulator off.
6
LDOSTAT
0: indicates that the core LDO voltage regulator is off.
1 (default) : indicates that the core LDO voltage regulator is on.
5
PWRDN
0 (default): all analog and digital circuitry and SPI logic are powered on.
1: powers down all analog and digital circuitry except for SPI logic.
4
Q DACOFF
0 (default): turns on Q DAC output current.
1: turns off Q DAC output current.
3
I DACOFF
0 (default): turns on I DAC output current.
1: turns off I DAC output current.
2
QCLKOFF
0 (default): turns on Q DAC clock.
1: turns off Q DAC clock.
1
ICLKOFF
0 (default): turns on I DAC clock.
1: turns off I DAC clock.
0
EXTREF
0 (default): turns on internal voltage reference.
1: powers down internal voltage reference (external reference required).
Data Control
0x02
7
TWOS
0 (default): unsigned binary input data format.
1: twos complement input data format.
5
IFIRST
0: pairing of data—Q first of pair on data input pads.
1 (default): pairing of data—I first of pair on data input pads.
4
IRISING
0: Q data latched on DCLKIO rising edge.
1 (default): I data latched on DCLKIO rising edge.
3
SIMULBIT
0 (default): allows simultaneous input and output enable on DCLKIO.
1: disallows simultaneous input and output enable on DCLKIO.
2
DCI_EN
Controls the use of the DCLKIO pad for data clock input.
0: data clock input disabled.
1 (default): data clock input enabled.
1
DCOSGL
Controls the use of the DCLKIO pad for data clock output.
0 (default): data clock output disabled.
1: data clock output enabled; regular strength driver.
0
DCODBL
Controls the use of the DCLKIO pad for data clock output.
0 (default): DCODBL data clock output disabled.
1: DCODBL data clock output enabled; paralleled with DCOSGL for 2× drive
current.
I DAC Gain
0x03
5:0
I DACGAIN[5:0]
DAC I fine gain adjustment; alters the full-scale current as shown in Figure 100.
Default IDACGAIN = 0x00.
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