參數(shù)資料
型號： AD9715-DPG2-EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 40/80頁
文件大?。?/td> 0K
描述： ADC 12BIT DUAL 40LFCSP
標準包裝： 1
系列： TxDAC®
DAC 的數(shù)量： 2
位數(shù)： 10
采樣率（每秒）： 125M
數(shù)據(jù)接口： 串行
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： 板
已用 IC / 零件： AD9715
AD9714/AD9715/AD9716/AD9717
Rev. A | Page 45 of 80
SELF-CALIBRATION
The AD9714/AD9715/AD9716/AD9717 have a self-calibration
feature that improves the DNL of the device. Performing a self-
calibration on the device improves device performance in low
frequency applications. The device performance in applications
where the analog output frequencies are above 5 MHz are generally
influenced more by dynamic device behavior than by DNL and,
in these cases, self-calibration is unlikely to provide much benefit.
The calibration clock frequency is equal to the DAC clock
divided by the division factor chosen by the DIVSEL value. Each
calibration clock cycle is between 32 and 2048 DAC input clock
cycles, depending on the value of DIVSEL[2:0] (Register 0x0E,
Bits[2:0]). The frequency of the calibration clock should be
between 0.5 MHz and 4 MHz for reliable calibrations. Best
results are obtained by setting DIVSEL[2:0] (Register 0x0E,
Bits[2:0]) to produce a calibration clock frequency between
these values. Separate self-calibration hardware is included
for each DAC. The DACs can be self-calibrated individually or
simultaneously.
To perform a device self-calibration, the following procedure
can be used:
1.
Write 0x00 to Register 0x12. This ensures that the
UNCALI and UNCALQ bits are reset.
2.
Set up a calibration clock between 0.5 MHz and 4 MHz
using DIVSEL[2:0], and then enable the calibration clock
by setting the CALCLK bit (Register 0x0E, Bit 3).
3.
Select the DAC(s) to self-calibrate by setting either Bit 4
(CALSELI) for the I DAC and/or Bit 5 (CALSELQ) for the
Q DAC in Register 0x0E. Note that each DAC contains
independent calibration hardware so that they can be
calibrated simultaneously.
4.
Start self-calibration by setting the CALEN bit (Register 0x12,
Bit 4). Wait approximately 300 calibration clock cycles.
5.
Check if the self-calibration has completed by reading
the CALSTATI bit (Bit 6) and CALSTATQ bit (Bit 7) in
Register 0x0F. Logic 1 indicates that the calibration has
completed.
6.
When the self-calibration has completed, write 0x00 to
Register 0x12.
7.
Disable the calibration clock by clearing the CALCLK bit
(Register 0x0E, Bit 3).
The AD9714/AD9715/AD9716/AD9717 allow reading and
writing of the calibration coefficients. There are 32 coefficients
in total. The read/write feature of the coefficients can be useful
for improving the results of the self-calibration routine by
averaging the results of several self-calibration cycles and
loading the averaged results back into the device.
To read the calibration coefficients, use the following steps:
1.
Select which DAC core to read by setting either Bit 4
(CALSELI) for the I DAC or Bit 5 (CALSELQ) for the
Q DAC in Register 0x0E. Write the address of the first
coefficient (0x01) to Register 0x10.
2.
Set the SMEMRD bit (Register 0x12, Bit 2) by writing 0x04
to Register 0x12.
3.
Read the 6-bit value of the first coefficient by reading the
contents of Register 0x11.
4.
Clear the SMEMRD bit by writing 0x00 to Register 0x12.
5.
Repeat Step 2 through Step 4 for each of the remaining 31
coefficients by incrementing the address by 1 for each read.
6.
Deselect the DAC core by clearing either Bit 4 (CALSELI)
for the I DAC or Bit 5 (CALSELQ) for the Q DAC in
Register 0x0E.
To write the calibration coefficients to the device, use the
following steps:
1.
Select which DAC core to write to by setting either Bit 4
(CALSELI) for the I DAC or Bit 5 (CALSELQ) for the Q
DAC in Register 0x0E.
2.
Set the SMEMWR bit (Register 0x12, Bit 3) by writing 0x08
to Register 0x12.
3.
Write the address of the first coefficient (0x01) to
Register 0x10.
4.
Write the value of the first coefficient to Register 0x11.
5.
Repeat Step 2 through Step 4 for each of the remaining 31
coefficients by incrementing the address by one for each
write.
6.
Clear the SMEMWR bit by writing 0x00 to Register 0x12.
7.
Deselect the DAC core by clearing either Bit 4 (CALSELI)
for the I DAC or Bit 5 (CALSELQ) for the Q DAC in
Register 0x0E.
相關(guān)PDF資料
PDF描述
MIC2076-2YM IC SW DISTRIBUTION 2CHAN 8SOIC
RBM10DSEF-S243 CONN EDGECARD 20POS .156 EYELET
VE-B6N-EY CONVERTER MOD DC/DC 18.5V 50W
ADR445ARZ-REEL7 IC VREF SERIES PREC 5V 8-SOIC
MIC2076-1YM IC DISTRIBUTION SW DUAL 8-SOIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9715-EBZ 制造商:Analog Devices 功能描述:DUAL 10 BIT LOW POWER CONVERTER - Boxed Product (Development Kits)
AD9716 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual, 8-/10-/12-/14-Bit Low Power Digital-to-Analog Converters
AD9716BCPZ 功能描述:IC DAC DUAL 12BIT LO PWR 40LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 標準包裝:1 系列:- 設(shè)置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND
AD9716BCPZRL7 功能描述:IC DAC DUAL 12BIT LO PWR 40LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 標準包裝:47 系列:- 設(shè)置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:*
AD9716-DPG2-EBZ 功能描述:ADC 12BIT DUAL 40LFCSP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*