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參數(shù)資料
| 型號： | AD9734-DPG2-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9734 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 1.2G |
| 數(shù)據(jù)接口： | 串行，SPI? |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板，軟件 |
| 已用 IC / 零件： | AD9734 |
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AD9734/AD9735/AD9736
Rev. A | Page 36 of 72
SERIAL PERIPHERAL INTERFACE
The AD973x serial port is a flexible, synchronous serial
communications port, allowing easy interface to many
industry-standard microcontrollers and microprocessors. The
serial I/O is compatible with most synchronous transfer
formats, including both the Motorola SPI and Intel SSR
protocols. The interface allows read/write access to all registers
that configure the AD973x. Single- or multiple-byte transfers
are supported, as well as most significant bit first (MSB-first) or
least significant bit first (LSB-first) transfer formats. The
AD973x serial interface port can be configured as a single pin
I/O (SDIO) or two unidirectional pins for in/out (SDIO/SDO).
SDO (PIN G14)
SDIO (PIN F14)
SCLK (PIN G13)
CSB (PIN F13)
AD973x
SPI PORT
04862-066
Figure 68. AD973x SPI Port
The AD973x can optionally be configured via external pins
rather than the serial interface. When the PIN_MODE input
(Pin L1) is high, the serial interface is disabled and its pins are
reassigned for direct control of the DAC. Specific functionality
is described in the Pin Mode Operation section.
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases to a communication cycle with the
AD973x. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD973x, coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD973x serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication
cycle. The Phase 1 instruction byte defines whether the
upcoming data transfer is read or write, the number of bytes in
the data transfer, and the starting register address for the first
byte of the data transfer. The first eight SCLK rising edges of
each communication cycle are used to write the instruction byte
into the AD973x.
The remaining SCLK edges are for Phase 2 of the communica-
tion cycle. Phase 2 is the actual data transfer between the
AD973x and the system controller. Phase 2 of the communica-
tion cycle is a transfer of 1, 2, 3, or 4 data bytes as determined
by the instruction byte. Using one multibyte transfer is the
preferred method. Single-byte data transfers are useful to
reduce CPU overhead when register access requires one byte
only. Registers change immediately upon writing to the last bit
of each transfer byte.
CSB (Chip Select) can be raised after each sequence of 8 bits
(except the last byte) to stall the bus. The serial transfer resumes
when CSB is lowered. Stalling on nonbyte boundaries resets
the SPI.
SHORT INSTRUCTION MODE (8-BIT INSTRUCTION)
The short instruction byte is shown in the following table:
MSB
LSB
I7
I6
I5
I4
I3
I2
I1
I0
R/W
N1
N0
A4
A3
A2
A1
A0
R/W, Bit 7 of the instruction byte, determines whether a read or
a write data transfer occurs after the instruction byte write.
Logic high indicates read operation. Logic 0 indicates a write
operation. N1, N0, Bit 6, and Bit 5 of the instruction byte
determine the number of bytes to be transferred during the data
transfer cycle. The bit decodes are shown in Table 20.
A4, A3, A2, A1, A0, Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the
instruction byte, determine which register is accessed during
the data transfer portion of the communications cycle. For
multibyte transfers, this address is the starting byte address. The
remaining register addresses are generated by the AD973x,
based on the LSBFIRST bit (Reg. 0, Bit 6).
Table 20. Byte Transfer Count
N1
N2
Description
0
Transfer 1 byte
0
1
Transfer 2 bytes
1
0
Transfer 3 bytes
1
Transfer 4 bytes
LONG INSTRUCTION MODE (16-BIT INSTRUCTION)
The long instruction bytes are shown in the following table:
MSB
LSB
I15
I14
I13
I12
I11
I10
I9
I8
R/W
N1
N0
A12
A11
A10
A9
A8
I7
I6
I5
I4
I3
I2
I1
I0
A7
A6
A5
A4
A3
A2
A1
A0
If LONG_INS = 1 (Reg. 0, Bit 4), the instruction byte is
extended to 2 bytes where the second byte provides an
additional 8 bits of address information. Address 0x00 to
Address 0x1F are equivalent in short and long instruction
modes. The AD973x does not use any addresses greater than 31
(0x1F), so always set LONG_INS = 0.
SERIAL INTERFACE PORT PIN DESCRIPTIONS
SCLK—Serial Clock
The serial clock pin is used to synchronize data to and from the
AD973x and to run the internal state machines. The maximum
frequency of SCLK is 20 MHz. All data input to the AD973x is
registered on the rising edge of SCLK. All data is driven out of
the AD973x on the rising edge of SCLK.
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