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參數(shù)資料
| 型號： | AD9734-DPG2-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9734 |
| 標準包裝： | 1 |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 1.2G |
| 數(shù)據(jù)接口： | 串行，SPI? |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板，軟件 |
| 已用 IC / 零件： | AD9734 |
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AD9734/AD9735/AD9736
Rev. A | Page 17 of 72
TERMINOLOGY
Linearity Error (Integral Nonlinearity or INL)
The maximum deviation of the actual analog output from the
ideal output, determined by a straight line drawn from zero to
full scale.
Differential Nonlinearity (DNL)
The measure of the variation in analog value, normalized to full
scale, associated with a 1 LSB change in digital input code.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero. For
IOUTA, 0 mA output is expected when the inputs are all 0s. For
IOUTB, 0 mA output is expected when all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits can
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Temperature Drift
Specified as the maximum change from the ambient (25°C)
value to the value at either TMIN or TMAX. For offset and gain
drift, the drift is reported in ppm of full-scale range (FSR) per
°C. For reference drift, the drift is reported in ppm per °C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion (THD)
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal. It is expressed as
a percentage or in decibels (dB).
Multitone Power Ratio
The spurious-free dynamic range containing multiple carrier
tones of equal amplitude. It is measured as the difference
between the rms amplitude of a carrier tone to the peak
spurious signal in the region of a removed tone.
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| AD9735BBC | 功能描述:IC DAC 12BIT 1.2GSPS 160CSPBGA RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設(shè)置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD9735BBCRL | 功能描述:IC DAC 12BIT 1.2GSPS 160CSPBGA RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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