參數(shù)資料
型號: AD9736BBCZRL
廠商: Analog Devices Inc
文件頁數(shù): 42/72頁
文件大?。?/td> 0K
描述: IC DAC 14BIT 1.2GSPS 160CSPBGA
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1,500
位數(shù): 14
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 550mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 160-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 160-CSPBGA(12x12)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電流,單極
采樣率(每秒): 1.2G
AD9734/AD9735/AD9736
Rev. A | Page 47 of 72
CROSS CONTROLLER REGISTERS
The AD973x differential output stage is adjustable to equalize
the charge injection into the positive and negative outputs. This
adjustment impacts certain performance characteristics, such as
harmonic distortion or IMD. System performance can be en-
hanced by adjusting the cross controller.
If the system is calibrated after manufacture, adjust the cross
controller offsets to provide optimum performance. To start,
increment DNDEL<5:0> (Reg. 11, Bits 5:0) while observing
HD2 (second harmonic distortion) and/or IMD to find the
desired optimum. If DNDEL does not influence the perform-
ance, set it to 0 and increment UPDEL<5:0> (Reg. 10, Bits 5:0).
Based on system characterization, set one of these controls to
the maximum value to yield the best performance.
Figure 85 shows the effect of UPDEL and DNDEL.
04862-083
INCREMENT DNDEL TO MOVE
THE CROSSING TOWARD THE
IDEAL VALUE
IDEAL DIFFERENTIAL OUTPUT
CROSSING ALIGNMENT
INCREMENT UPDEL TO MOVE
THE CROSSING TOWARD THE
IDEAL VALUE
Figure 85. Effect of UPDEL and DNDEL
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