參數(shù)資料
型號： AD9740ACP-PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 31/32頁
文件大小： 0K
描述： BOARD EVAL FOR AD9740ACP
產品培訓模塊： DAC Architectures
標準包裝： 1
系列： TxDAC®
DAC 的數(shù)量： 1
位數(shù)： 10
采樣率（每秒）： 210M
數(shù)據接口： 并聯(lián)
設置時間： 11ns
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： 板
已用 IC / 零件： AD9740
相關產品： AD9740ARZ-ND - IC DAC 10BIT 210MSPS 28-SOIC
AD9740ARUZ-ND - IC DAC 10BIT 210MSPS 28-TSSOP
AD9740ARUZRL7-ND - IC DAC 10BIT 210MSPS 28-TSSOP
AD9740ACPZRL7-ND - IC DAC 10BIT 210MSPS 32-LFCSP
AD9740ARZRL-ND - IC DAC 10BIT 210MSPS 28-SOIC
AD9740ACPZ-ND - IC DAC 10BIT 210MSPS 32-LFCSP
AD9740ARURL7-ND - IC DAC 10BIT 210MSPS 28-TSSOP
AD9740ARU-ND - IC DAC 10BIT 210MSPS 28-TSSOP
AD9740
Rev. B | Page 8 of 32
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NC = NO CONNECT
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DB8
DB7
DB6
DB3
DB4
DB5
(MSB) DB9
DVDD
DCOM
MODE
IOUTA
RESERVED
AVDD
DB2
DB1
DB0
NC
IOUTB
ACOM
NC
SLEEP
NC
REFLO
REFIO
FS ADJ
CLOCK
AD9740
TOP VIEW
(Not to Scale)
02911-
003
Figure 3. 28-Lead SOIC and TSSOP Pin Configuration
PIN 1
INDICATOR
NC = NO CONNECT
1
DB3
2
DB2
3
DVDD
4
DB1
5
DB0
6
NC
7
NC
8
NC
24 FS ADJ
23 REFIO
22 ACOM
21 IOUTA
20 IOUTB
19 ACOM
18 AVDD
17 AVDD
9
N
C
1
0
D
C
O
M
11
C
L
K
V
D
12
C
L
K
+
13
C
L
K
–
14
C
L
K
C
O
M
15
C
M
O
D
E
1
6
M
O
D
E
32
D
B
4
3
1
D
B
5
3
0
D
B
6
2
9
D
B
7
2
8
D
B
8
2
7
D
B
9
(M
S
B
)
26
D
C
O
M
25
S
L
E
P
TOP VIEW
(Not to Scale)
AD9740
02911-
004
Figure 4. 32-Lead LFCSP Pin Configuration
Table 5. Pin Function Descriptions
SOIC/TSSOP
Pin No.
LFCSP
Pin No.
Mnemonic
Description
1
27
DB9 (MSB)
Most Significant Data Bit (MSB).
2 to 9
28 to 32, 1, 2, 4
DB8 to DB1
Data Bits 8 to 1.
10
5
DB0 (LSB)
Least Significant Data Bit (LSB).
11 to 14, 19
6 to 9
NC
No Internal Connection.
15
25
SLEEP
Power-Down Control Input. Active high. Contains active pull-down circuit; it can be
left unterminated if not used.
16
N/A
REFLO
Reference Ground when Internal 1.2 V Reference Used. Connect to ACOM for both
internal and external reference operation modes.
17
23
REFIO
Reference Input/Output. Serves as reference input when using external reference.
Serves as 1.2 V reference output when using internal reference. Requires 0.1 μF capacitor
to ACOM when using internal reference.
18
24
FS ADJ
Full-Scale Current Output Adjust.
20
19, 22
ACOM
Analog Common.
21
20
IOUTB
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
22
21
IOUTA
DAC Current Output. Full-scale current when all data bits are 1s.
23
N/A
RESERVED
Reserved. Do Not Connect to Common or Supply.
24
17, 18
AVDD
Analog Supply Voltage (3.3 V).
25
16
MODE
Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement.
N/A
15
CMODE
Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+
and float CLK–). Connect to CLKVDD for differential receiver. Float for PECL receiver
(terminations on-chip).
26
10, 26
DCOM
Digital Common.
27
3
DVDD
Digital Supply Voltage (3.3 V).
28
N/A
CLOCK
Clock Input. Data latched on positive edge of clock.
N/A
12
CLK+
Differential Clock Input.
N/A
13
CLK
Differential Clock Input.
N/A
11
CLKVDD
Clock Supply Voltage (3.3 V).
N/A
14
CLKCOM
Clock Common.
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