參數(shù)資料
型號(hào)： AD9740ACP-PCBZ
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 5/32頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9740ACP
產(chǎn)品培訓(xùn)模塊： DAC Architectures
標(biāo)準(zhǔn)包裝： 1
系列： TxDAC®
DAC 的數(shù)量： 1
位數(shù)： 10
采樣率（每秒）： 210M
數(shù)據(jù)接口： 并聯(lián)
設(shè)置時(shí)間： 11ns
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： 板
已用 IC / 零件： AD9740
相關(guān)產(chǎn)品： AD9740ARZ-ND - IC DAC 10BIT 210MSPS 28-SOIC
AD9740ARUZ-ND - IC DAC 10BIT 210MSPS 28-TSSOP
AD9740ARUZRL7-ND - IC DAC 10BIT 210MSPS 28-TSSOP
AD9740ACPZRL7-ND - IC DAC 10BIT 210MSPS 32-LFCSP
AD9740ARZRL-ND - IC DAC 10BIT 210MSPS 28-SOIC
AD9740ACPZ-ND - IC DAC 10BIT 210MSPS 32-LFCSP
AD9740ARURL7-ND - IC DAC 10BIT 210MSPS 28-TSSOP
AD9740ARU-ND - IC DAC 10BIT 210MSPS 28-TSSOP
AD9740
Rev. B | Page 13 of 32
FUNCTIONAL DESCRIPTION
Figure 22 shows a simplified block diagram of the AD9740. The
AD9740 consists of a DAC, digital control logic, and full-scale
output current control. The DAC contains a PMOS current
source array capable of providing up to 20 mA of full-scale
current (IOUTFS). The array is divided into 31 equal currents that
make up the five most significant bits (MSBs). The next four
bits, or middle bits, consist of 15 equal current sources whose
value is 1/16 of an MSB current source. The remaining LSBs are
binary weighted fractions of the middle bits current sources.
Implementing the middle and lower bits with current sources,
instead of an R-2R ladder, enhances its dynamic performance
for multitone or low amplitude signals and helps maintain the
DAC’s high output impedance (that is, >100 kΩ).
All of these current sources are switched to one or the other of
the two output nodes (that is, IOUTA or IOUTB) via PMOS
differential current switches. The switches are based on the
architecture that was pioneered in the AD9764 family, with
further refinements to reduce distortion contributed by the
switching transient. This switch architecture also reduces
various timing errors and provides matching complementary
drive signals to the inputs of the differential current switches.
The analog and digital sections of the AD9740 have separate
power supply inputs (that is, AVDD and DVDD) that can
operate independently over a 2.7 V to 3.6 V range. The digital
section, which is capable of operating at a clock rate of up to
210 MSPS, consists of edge-triggered latches and segment
decoding logic circuitry. The analog section includes the PMOS
current sources, the associated differential switches, a 1.2 V
band gap voltage reference, and a reference control amplifier.
The DAC full-scale output current is regulated by the reference
control amplifier and can be set from 2 mA to 20 mA via an
external resistor, RSET, connected to the full-scale adjust
(FS ADJ) pin. The external resistor, in combination with both
the reference control amplifier and voltage reference, VREFIO, sets
the reference current, IREF, which is replicated to the segmented
current sources with the proper scaling factor. The full-scale
current, IOUTFS, is 32 times IREF.
REFERENCE OPERATION
The AD9740 contains an internal 1.2 V band gap reference. The
internal reference cannot be disabled, but can be easily overridden
by an external reference with no effect on performance. Figure 23
shows an equivalent circuit of the band gap reference. REFIO
serves as either an output or an input depending on whether
the internal or an external reference is used. To use the internal
reference, simply decouple the REFIO pin to ACOM with a
0.1 μF capacitor and connect REFLO to ACOM via a resistance
less than 5 Ω. The internal reference voltage is present at
REFIO. If the voltage at REFIO is to be used anywhere else in
the circuit, then an external buffer amplifier with an input bias
current of less than 100 nA should be used. An example of the
use of the internal reference is shown in Figure 24.
AVDD
7k
84A
REFLO
REFIO
0
291
1-
05
7
Figure 23. Equivalent Circuit of Internal Reference
150pF
1.2V REF
AVDD
REFLO
CURRENT
SOURCE
ARRAY
3.3V
REFIO
FS ADJ
2k
Ω
0.1
μF
AD9740
ADDITIONAL
LOAD
OPTIONAL
EXTERNAL
REF BUFFER
02911-
022
Figure 24. Internal Reference Configuration
An external reference can be applied to REFIO, as shown in
Figure 25. The external reference can provide either a fixed
reference voltage to enhance accuracy and drift performance
or a varying reference voltage for gain control. Note that the
0.1 μF compensation capacitor is not required because the
internal reference is overridden, and the relatively high input
impedance of REFIO minimizes any loading of the external
reference.
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