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參數(shù)資料
| 型號： | AD9741-DPG2-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC DUAL 8BIT 200MSPS 72LFCSP |
| 設計資源： | AD9747/6/5/3/1 DPG2 Eval Brd Schematic |
| 標準包裝： | 1 |
| DAC 的數(shù)量： | 2 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 250M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9741 |
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Data Sheet
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. A | Page 19 of 28
internally by the serial port controller by decrementing from
the specified address. For LSB-first format, the specified address
is a beginning address or the least significant address in the
current cycle. Remaining register addresses for multiple byte
data transfers are generated internally by the serial port
controller by incrementing from the specified address.
MSB/LSB TRANSFERS
The serial port can support both MSB-first and LSB-first data
formats. This functionality is controlled by Register 0x00, Bit 6.
The default is Logic 0, which is MSB-first format.
When using MSB-first format (LSBFIRST = 0), the instruction
and data bit must be written from MSB to LSB. Multibyte data
transfers in MSB-first format start with an instruction byte that
includes the register address of the most significant data byte.
Subsequent data bytes are loaded into sequentially lower
address locations. In MSB-first mode, the serial port internal
address generator decrements for each byte of the multibyte
data transfer.
When using LSB-first format (LSBFIRST = 1), the instruction
and data bit must be written from LSB to MSB. Multibyte data
transfers in LSB-first format start with an instruction byte that
includes the register address of the least significant data byte.
Subsequent data bytes are loaded into sequentially higher
address locations. In LSB-first mode, the serial port internal
address generator increments for each byte of the multibyte
data transfer.
Use of a single-byte transfer when changing the serial port data
format is recommended to prevent unexpected device behavior.
SERIAL INTERFACE PORT PIN DESCRIPTIONS
Chip Select Bar (CSB)
Active low input starts and gates a communication cycle. It
allows more than one device to be used on the same serial
communication lines. CSB must stay low during the entire
communication cycle. Incomplete data transfers are aborted
anytime the CSB pin goes high. SDO and SDIO pins go to a
high impedance state when this input is high.
Serial Clock (SCLK)
The serial clock pin is used to synchronize data to and from the
device and to run the internal state machines. The maximum
frequency of SCLK is 40 MHz. All data input is registered on
the rising edge of SCLK. All data is driven out on the falling
edge of SCLK.
Serial Data I/O (SDIO)
Data is always written into the device on this pin. However,
SDIO can also function as a bidirectional data output line.
The configuration of this pin is controlled by Register 0x00,
Bit 7. The default is Logic 0, which configures the SDIO pin
as unidirectional.
Serial Data Out (SDO)
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. The configuration of this
pin is controlled by Register 0x00, Bit 7. If this bit is set to a
Logic 1, the SDO pin does not output data and is set to a high
impedance state.
R/W N1
N0
A4 A3
A2
A1
A0
D7 D6N D5N
D00
D10
D20
D30
D7 D6N D5N
D00
D10
D20
D30
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
06569-
014
Figure 23. Serial Register Interface—MSB First
A0
A1
A2
A3 A4
N0
N1 R/W D00 D10 D20
D7N
D6N
D5N
D4N
D00 D10 D20
D7N
D6N
D5N
D4N
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
06569-
015
Figure 24. Serial Register Interface Timing—LSB First
INSTRUCTION BIT 6
INSTRUCTION BIT 7
CSB
SCLK
SDIO
tS
tDS
tDH
tPWH
tPWL
fSCLK–1
06569-
016
Figure 25. Timing Diagram for SPI Register Write
DATA BIT N – 1
DATA BIT N
CSB
SCLK
SDIO
SDO
tDV
06569-
017
Figure 26. Timing Diagram for SPI Register Read
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9741-EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD9741 制造商:Analog Devices 功能描述:DUAL 8BIT, 200 MSPS D-A CONVERTER - Bulk |
| AD9742 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Analog Devices: Data Converters: DAC 12-Bit, 10 ns to 100 ns Converters Selection Table |
| AD9742ACP | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 12-bit 32-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:12-BIT 165 MSPS TXDAC D/A CONVERTER - Bulk 制造商:Analog Devices 功能描述:IC 12-BIT DAC |
| AD9742ACP-PCB | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9742 12BIT, 165MSPS TXDAC D/A CNVRTR - Bulk |
| AD9742ACP-PCBZ | 功能描述:BOARD EVAL FOR AD9742ACP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC® 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
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