參數(shù)資料
型號(hào)： AD9745BCPZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 11/28頁(yè)
文件大小： 0K
描述： IC DAC DUAL 12B 250MSPS 72-LFCSP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 12
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 345mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 72-LFCSP
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 4 電流，單極
采樣率（每秒）： 250M
Data Sheet
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. A | Page 19 of 28
internally by the serial port controller by decrementing from
the specified address. For LSB-first format, the specified address
is a beginning address or the least significant address in the
current cycle. Remaining register addresses for multiple byte
data transfers are generated internally by the serial port
controller by incrementing from the specified address.
MSB/LSB TRANSFERS
The serial port can support both MSB-first and LSB-first data
formats. This functionality is controlled by Register 0x00, Bit 6.
The default is Logic 0, which is MSB-first format.
When using MSB-first format (LSBFIRST = 0), the instruction
and data bit must be written from MSB to LSB. Multibyte data
transfers in MSB-first format start with an instruction byte that
includes the register address of the most significant data byte.
Subsequent data bytes are loaded into sequentially lower
address locations. In MSB-first mode, the serial port internal
address generator decrements for each byte of the multibyte
data transfer.
When using LSB-first format (LSBFIRST = 1), the instruction
and data bit must be written from LSB to MSB. Multibyte data
transfers in LSB-first format start with an instruction byte that
includes the register address of the least significant data byte.
Subsequent data bytes are loaded into sequentially higher
address locations. In LSB-first mode, the serial port internal
address generator increments for each byte of the multibyte
data transfer.
Use of a single-byte transfer when changing the serial port data
format is recommended to prevent unexpected device behavior.
SERIAL INTERFACE PORT PIN DESCRIPTIONS
Chip Select Bar (CSB)
Active low input starts and gates a communication cycle. It
allows more than one device to be used on the same serial
communication lines. CSB must stay low during the entire
communication cycle. Incomplete data transfers are aborted
anytime the CSB pin goes high. SDO and SDIO pins go to a
high impedance state when this input is high.
Serial Clock (SCLK)
The serial clock pin is used to synchronize data to and from the
device and to run the internal state machines. The maximum
frequency of SCLK is 40 MHz. All data input is registered on
the rising edge of SCLK. All data is driven out on the falling
edge of SCLK.
Serial Data I/O (SDIO)
Data is always written into the device on this pin. However,
SDIO can also function as a bidirectional data output line.
The configuration of this pin is controlled by Register 0x00,
Bit 7. The default is Logic 0, which configures the SDIO pin
as unidirectional.
Serial Data Out (SDO)
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. The configuration of this
pin is controlled by Register 0x00, Bit 7. If this bit is set to a
Logic 1, the SDO pin does not output data and is set to a high
impedance state.
R/W N1
N0
A4 A3
A2
A1
A0
D7 D6N D5N
D00
D10
D20
D30
D7 D6N D5N
D00
D10
D20
D30
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
06569-
014
Figure 23. Serial Register Interface—MSB First
A0
A1
A2
A3 A4
N0
N1 R/W D00 D10 D20
D7N
D6N
D5N
D4N
D00 D10 D20
D7N
D6N
D5N
D4N
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
06569-
015
Figure 24. Serial Register Interface Timing—LSB First
INSTRUCTION BIT 6
INSTRUCTION BIT 7
CSB
SCLK
SDIO
tS
tDS
tDH
tPWH
tPWL
fSCLK–1
06569-
016
Figure 25. Timing Diagram for SPI Register Write
DATA BIT N – 1
DATA BIT N
CSB
SCLK
SDIO
SDO
tDV
06569-
017
Figure 26. Timing Diagram for SPI Register Read
相關(guān)PDF資料
PDF描述
VI-25R-IV-F2 CONVERTER MOD DC/DC 7.5V 150W
VI-25R-IV-F1 CONVERTER MOD DC/DC 7.5V 150W
VI-25P-IV-F4 CONVERTER MOD DC/DC 13.8V 150W
VI-24M-MW-B1 CONVERTER MOD DC/DC 10V 100W
DAC8562FS-REEL IC DAC 12BIT PARALLEL 5V 20-SOIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9745-DPG2-EBZ 功能描述:IC DAC DUAL 12BIT 72LFCSP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
AD9745-EBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual 8-/10-/12-/14-/16-Bit 250 MSPS Digital-to-Analog Converters
AD9746 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual 8-/10-/12-/14-/16-Bit 250 MSPS Digital-to-Analog Converters
AD9746BCPZ 功能描述:IC DAC DUAL 14B 250MSPS 72LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k
AD9746BCPZRL 功能描述:IC DAC DUAL 14B 250MSPS 72-LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*