F
參數(shù)資料
型號(hào)： AD9745BCPZRL
廠商： Analog Devices Inc
文件頁數(shù)： 18/28頁
文件大?。?/td> 0K
描述： IC DAC DUAL 12B 250MSPS 72-LFCSP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 12
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 345mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 72-LFCSP
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 4 電流，單極
采樣率（每秒）： 250M
AD9741/AD9743/AD9745/AD9746/AD9747
Data Sheet
Rev. A | Page 25 of 28
0
–10
–20
–30
–40
T
(f)
(d
B
)
0.5
1.5
2
FS
NORMAL
RZ
MIX
06569-
027
Figure 36. Transfer Function for Each Analog Operating Mode
AUXILIARY DACS
Two auxiliary DACs are provided on the AD9741/AD9743/
AD9745/AD9746/AD9747. A functional diagram is shown
in Figure 37. The auxiliary DACs are current output devices
with two output pins, AUXP and AUXN. The active pin can
be programmed to either source or sink current. When either
sinking or sourcing, the full-scale current magnitude is 2 mA.
The available compliance range at the auxiliary DAC outputs
depends on whether the output is configured to a sink or source
current. When sourcing current, the compliance voltage is 0 V
to 1.6 V, but when sinking current, the output compliance
voltage reduces to 0.8 V to 1.6 V. Either output can be used, but
only one output of the auxiliary DAC (P or N) is active at any
time. The inactive pin is always in a high impedance state
(>100 kΩ).
06569-
035
VBIAS
AUXP
AUXN
SINK
OR
SOURCE
POSITIVE
OR
NEGATIVE
0mA
TO
2mA
0mA
TO
2mA
Figure 37. Auxiliary DAC Functional Diagram
In a single side band transmitter application, the combination of
the input referred dc offset voltage of the quadrature modulator
and the DAC output offset voltage can result in local oscillator
(LO) feedthrough at the modulator output, which degrades
system performance. The auxiliary DACs can be used to remove
the dc offset and the resulting LO feedthrough. The circuit
configuration for using the auxiliary DACs for performing
dc offset correction depends on the details of the DAC and
modulator interface. An example of a dc-coupled configuration
with low-pass filtering is outlined in the Power Dissipation
section.
AD9747
AUX
DAC1 OR
DAC2
AD9747
DAC1 OR
DAC2
25 TO 50
QUAD MOD
I OR Q INPUTS
QUADRATURE
MODULATOR V+
25 TO 50
06569-
029
OPTIONAL
PASSIVE
FILTERING
Figure 38. DAC DC Coupled to Quadrature Modulator with Passive DC Shift
POWER DISSIPATION
Figure 39 shows the power dissipation and current draw of the
devices have a quiescent power dissipation of about 190 mW.
Most of this comes from the AVDD33 supply. Total power
dissipation increases about 50% as the clock rate is increased
to the maximum clock rate of 250 MHz.
350
310
270
230
190
150
P
TO
TA
L
(
mW
)
0
50
100
150
200
250
fDAC (MHz)
06569-
030
25
75
125
175
225
fOUT = DC
fOUT = NYQUIST
Figure 39. AD9747 Power Dissipation vs. fDAC
15
12
9
6
3
0
I DV
DD3
3
(
mA)
0
50
100
150
200
250
fDAC (MHz)
06569-
031
25
75
125
175
225
AD9747
AD9741
Figure 40. DVDD33 Current vs. fDAC
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AD9746 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual 8-/10-/12-/14-/16-Bit 250 MSPS Digital-to-Analog Converters
AD9746BCPZ 功能描述:IC DAC DUAL 14B 250MSPS 72LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k
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