I DV DD1 8 ( mA) 0" />
參數(shù)資料
型號(hào)： AD9747BCPZRL
廠商： Analog Devices Inc
文件頁數(shù)： 19/28頁
文件大小： 0K
描述： IC DAC DUAL 16B 250MSPS 72-LFCSP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 16
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 345mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 72-LFCSP
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 4 電流，單極
采樣率（每秒）： 250M
AD9741/AD9743/AD9745/AD9746/AD9747
Data Sheet
Rev. A | Page 26 of 28
30
24
18
12
6
0
I DV
DD1
8
(
mA)
0
50
100
150
200
250
fDAC (MHz)
06569-
032
25
75
125
175
225
AD9747
AD9741
Figure 41. DVDD18 Current vs. fDAC
15
13
11
9
7
5
I CV
DD1
8
(
mA)
0
50
100
150
200
250
fDAC (MHz)
06569-
033
25
75
125
175
225
Figure 42. CVDD18 Current vs. fDAC
Figure 43 shows the power consumption for each power supply
domain as well as the total power consumption. Individual bars
within each group display the power in full active mode (blue)
vs. power for five increasing levels of power-down.
06569-
045
P
DI
S
(
mW
)
0
50
100
150
200
250
300
350
AVDD33
DVDD18
CVDD18
DVDD33
TOT PWR
FULL ACTIVE
DCO OFF
AUX OFF
DAC OFF
CLK OFF
BIAS OFF
Figure 43. Power Dissipation vs. Power-Down Mode
The overall power consumption is dominated by AVDD33 and
significant power savings can be achieved simply by disabling
the DAC outputs. Also, disabling the DAC outputs is a signifi-
cant way to conserve power and still maintain a fast wake-up
time. Full power-down disables all circuitry for minimum
power consumption. Note, however, that even in full power-
down, there is a small power draw (25 mW) due to incoming
data activity. To lower power consumption to near zero, all
incoming data activity must be halted.
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