TMIN
參數(shù)資料
型號: AD9747BCPZRL
廠商: Analog Devices Inc
文件頁數(shù): 26/28頁
文件大小: 0K
描述: IC DAC DUAL 16B 250MSPS 72-LFCSP
產(chǎn)品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 2,000
位數(shù): 16
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
功率耗散(最大): 345mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 72-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 72-LFCSP
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 4 電流,單極
采樣率(每秒): 250M
Data Sheet
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. A | Page 7 of 28
DIGITAL AND TIMING SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, full-scale digital input, maximum
sample rate, unless otherwise noted.
Parameter
Min
Typ
Max
Unit
DAC CLOCK INPUTS (CLKP, CLKN)
Differential Peak-to-Peak Voltage
400
800
1600
mV
Single-Ended Peak-to-Peak Voltage
800
mV
Common-Mode Voltage
300
400
500
mV
Input Current
1
μA
Input Frequency
250
MHz
DATA CLOCK OUTPUT (DCO)
Output Voltage High
2.4
V
Output Voltage Low
0.4
V
Output Current
10
mA
DAC Clock to Data Clock Output Delay (tDCO)
2.0
2.2
2.8
ns
DATA PORT INPUTS
Input Voltage High
2.0
V
Input Voltage Low
0.8
V
Input Current
1
μA
Data to DAC Clock Setup Time (tDBS Dual-Port Mode)
400
ps
Data to DAC Clock Hold Time (tDBH Dual-Port Mode)
1200
ps
DAC Clock to Analog Output Data Latency (Dual-Port Mode)
7
Cycles
Data or IQSEL Input to DAC Clock Setup Time (tDBS Single-Port Mode)
400
ps
Data or IQSEL Input to DAC Clock Hold Time (tDBH Single-Port Mode)
1200
ps
DAC Clock to Analog Output Data Latency (Single-Port Mode)
8
Cycles
SERIAL PERIPHERAL INTERFACE
SCLK Frequency (fSCLK)
40
MHz
SCLK Pulse Width High (tPWH)
10
ns
SCLK Pulse Width Low (tPWL)
10
ns
CSB to SCLK Setup Time (tS)
1
ns
CSB to SCLK Hold Time (tH)
0
ns
SDIO to SCLK Setup Time (tDS)
1
ns
SDIO to SCLK Hold Time (tDH)
0
ns
SCLK to SDIO/SDO Data Valid Time (tDV)
1
ns
RESET Pulse Width High
10
ns
WAKE-UP TIME AND OUTPUT LATENCY
From DAC Outputs Disabled
200
μs
From Full Device Power-Down
1200
μs
DAC Clock to Analog Output Latency (Dual-Port Mode)
7
Cycles
DAC Clock to Analog Output Latency (Single-Port Mode)
8
Cycles
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