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參數(shù)資料
| 型號： | AD974BRSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS 16BIT 4CH 200KSPS 28-SSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS） |
| 分辨率（位）： | 16 b |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 串行 |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
| 配用： | EVAL-AD974CB-ND - BOARD EVAL FOR AD974 |
REV. A
AD974
–10–
EXTERNAL DISCONTINUOUS CLOCK DATA READ
DURING CONVERSION WITH SYNC OUTPUT
GENERATED
Figure 7 illustrates the method by which data from conversion
“n-1” can be read during conversion “n” while using a discon-
tinuous external clock, with the generation of a SYNC output.
What permits the generation of a SYNC output is a transition of
DATACLK while either
CS is High or while both CS and R/C
are low. In Figure 7 a conversion is initiated by taking R/
C low
with
CS tied low. While this condition exists a transition of
DATACLK, clock pulse #0, will enable the generation of a
SYNC pulse. Less then 83 ns after R/
C is taken low the BUSY
output will go low to indicate that the conversion process has
begun. Figure 7 shows R/
C then going high and after a delay of
greater than 15 ns (t15) clock pulse #1 can be taken high to
request the SYNC output. The SYNC output will appear ap-
proximately 40 ns after this rising edge and will be valid on the
falling edge of clock pulse #1 and the rising edge of clock pulse
#2. The MSB will be valid approximately 40 ns after the rising
edge of clock pulse #2 and can be latched off either the falling
edge of clock pulse #2 or the rising edge of clock pulse #3. The
LSB will be valid on the falling edge of clock pulse #17 and the
rising edge of clock pulse #18.
Data should be clocked out during the first half of
BUSY to
avoid degrading conversion performance. This requires use of a
10 MHz DATACLK or greater, with data being read out as
soon as the conversion process begins.
t12
EXT
DATACLK
R/
C
BUSY
SYNC
DATA
0
t13
t14
t15
t22
t20
t1
t2
t17
t12
t18
BIT 15
(MSB)
BIT 14
BIT 0
(LSB)
1234
17
18
Figure 7. Conversion and Read Timing for Reading Previous Conversion Results During a Conversion
Using External Discontinuous Data Clock (EXT/
INT Set to Logic High, CS Set to Logic Low)
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| AD974BRZ | 功能描述:IC DAS 16BIT 4CH 200KSPS 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Basics 標(biāo)準(zhǔn)包裝:1 系列:- 類型:電機(jī)控制 分辨率（位）:12 b 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，并聯(lián) 電壓電源:單電源 電源電壓:2.7 V ~ 3.6 V，4.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:100-TQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:剪切帶 (CT) 其它名稱:296-18373-1 |
| AD9750 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 125 MSPS High Performance TxDAC D/A Converter |
| AD9750AR | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 10-bit 28-Pin SOIC W 制造商:Analog Devices 功能描述:DAC SGL 10-BIT 28SOIC - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:10 BIT 12500 MSPS+ TXDAC D/A CONVERTER - Bulk 制造商:Analog Devices 功能描述:0BIT DAC POLY FUSE 9750 SOIC28 |
| AD9750ARRL | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 10-bit 28-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:10 BIT 125 MSPS+ TXDAC D/A CONVERTER - Bulk |
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