- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9502 > AD974BRSZ (Analog Devices Inc)IC DAS 16BIT 4CH 200KSPS 28-SSOP PDF資料下載
參數(shù)資料
| 型號： | AD974BRSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS 16BIT 4CH 200KSPS 28-SSOP |
| 標準包裝： | 1 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS） |
| 分辨率（位）： | 16 b |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 串行 |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
| 配用： | EVAL-AD974CB-ND - BOARD EVAL FOR AD974 |
REV. A
AD974
–11–
EXTERNAL CONTINUOUS CLOCK DATA READ AFTER
CONVERSION WITH SYNC OUTPUT GENERATED
Figure 8 illustrates the method by which data from conversion
“n” can be read after the conversion is complete using a con-
tinuous external clock, with the generation of a SYNC output.
What permits the generation of a SYNC output is a transition of
DATACLK either while
CS is high or while both CS and R/C are
low.
With a continuous clock the
CS pin cannot be tied low as it
could be with a discontinuous clock. Use of a continuous clock,
while a conversion is occurring, can increase the DNL and
Transition Noise of the AD974.
After a conversion is complete, indicated by
BUSY returning
high, the result of that conversion can be read while
CS is low
and R/
C is high. In Figure 8 clock pulse #0 is used to enable the
generation of a SYNC pulse. The SYNC pulse is actually clocked
out approximately 40 ns after the rising edge of clock pulse #1.
The SYNC pulse will be valid on the falling edge of clock pulse
#1 and the rising edge of clock pulse #2. The MSB will be valid
on the falling edge of clock pulse #2 and the rising edge of clock
pulse #3. The LSB will be valid on the falling edge of clock
pulse #17 and the rising edge of clock pulse #18.
When reading data after the conversion is complete, with the
highest frequency permitted for DATACLK (15.15 MHz) the
maximum possible throughput is approximately 195 kHz and
not the rated 200 kHz.
EXT
DATACLK
CS
R/
C
BUSY
SYNC
DATA
0
t12
t13
t14
1
2
3
4
17
18
t1
t15
t10
t2
t16
t17
t12
t18
t19
BIT 15
(MSB)
BIT 14
BIT 0
(LSB)
Figure 8. Conversion and Read Timing Using an External Continuous Data Clock (EXT/
INT Set to Logic High)
相關PDF資料 |
PDF描述 |
|---|---|
| V110A24M300BF2 | CONVERTER MOD DC/DC 24V 300W |
| AD974ANZ | IC DAS 16BIT 4CH 200KSPS 28DIP |
| VI-B4R-MY-S | CONVERTER MOD DC/DC 7.5V 50W |
| VE-B31-IU | CONVERTER MOD DC/DC 12V 200W |
| VI-B3X-IU | CONVERTER MOD DC/DC 5.2V 200W |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD974BRZ | 功能描述:IC DAS 16BIT 4CH 200KSPS 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓模塊:Data Converter Basics 標準包裝:1 系列:- 類型:電機控制 分辨率（位）:12 b 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，并聯(lián) 電壓電源:單電源 電源電壓:2.7 V ~ 3.6 V，4.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:100-TQFP 供應商設備封裝:100-TQFP（14x14） 包裝:剪切帶 (CT) 其它名稱:296-18373-1 |
| AD9750 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 125 MSPS High Performance TxDAC D/A Converter |
| AD9750AR | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 10-bit 28-Pin SOIC W 制造商:Analog Devices 功能描述:DAC SGL 10-BIT 28SOIC - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:10 BIT 12500 MSPS+ TXDAC D/A CONVERTER - Bulk 制造商:Analog Devices 功能描述:0BIT DAC POLY FUSE 9750 SOIC28 |
| AD9750ARRL | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 10-bit 28-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:10 BIT 125 MSPS+ TXDAC D/A CONVERTER - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。