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參數(shù)資料
| 型號： | AD9751ASTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT 300MSPS 48-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TxDAC+® |
| 設(shè)置時間： | 11ns |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 165mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 300M |
| 產(chǎn)品目錄頁面： | 785 (CN2011-ZH PDF) |
| 配用： | AD9751-EB-ND - BOARD EVAL FOR AD9751 |
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REV. C
AD9751
–17–
The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both IOUTA and IOUTB. The complementary voltages appearing
at IOUTA and IOUTB (i.e., VOUTA and VOUTB) swing symmetrically
around ACOM and should be maintained with the specified
output compliance range of the AD9751. A differential resistor,
RDIFF, may be inserted into applications where the output of the
transformer is connected to the load, RLOAD, via a passive recon-
struction filter or cable. RDIFF is determined by the transformer’s
impedance ratio and provides the proper source termination that
results in a low VSWR.
DIFFERENTIAL COUPLING USING AN OP AMP
An op amp can also be used to perform a differential-to-
single-ended conversion, as shown in Figure 21. The AD9751
is configured with two equal load resistors, RLOAD, of 25
. The
differential voltage developed across IOUTA and IOUTB is con-
verted to a single-ended signal via the differential op amp
configuration. An optional capacitor can be installed across
IOUTA and IOUTB, forming a real pole in a low-pass filter. The
addition of this capacitor also enhances the op amp’s distortion
performance by preventing the DAC’s high slewing output from
overloading the op amp’s input.
AD9751
IOUTA
IOUTB
COPT
500
225
500
25
AD8047
Figure 21. DC Differential Coupling Using an Op Amp
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the dif-
ferential op amp circuit using the AD8047 is configured to
provide some additional signal gain. The op amp must operate
from a dual supply since its output is approximately
± 1.0 V.
A high speed amplifier capable of preserving the differential
performance of the AD9751, while meeting other system-
level objectives (i.e., cost, power), should be selected. The op
amp’s differential gain, gain setting resistor values, and full-
scale output swing capabilities should all be considered when
optimizing this circuit.
The differential circuit shown in Figure 22 provides the nec-
essary level-shifting required in a single-supply system. In this
case, AVDD, which is the positive analog supply for both the
AD9751 and the op amp, is also used to level-shift the differ-
ential output of the AD9751 to midsupply (i.e., AVDD/2). The
AD8041 is a suitable op amp for this application.
AD9751
IOUTA
IOUTB
COPT
500
225
1k
25
AD8041
1k
AVDD
Figure 22. Single-Supply DC Differential Coupled Circuit
SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT
Figure 23 shows the AD9751 configured to provide a unipolar
output range of approximately 0 V to 0.5 V for a doubly-termi-
nated 50
cable, since the nominal full-scale current, I
OUTFS, of
20 mA flows through the equivalent RLOAD of 25
. In this case,
RLOAD represents the equivalent load resistance seen by IOUTA or
IOUTB. The unused output (IOUTA or IOUTB) can be connected to
ACOM directly or via a matching RLOAD. Different values of
IOUTFS and RLOAD can be selected as long as the positive com-
pliance range is adhered to. One additional consideration in
this mode is the integral nonlinearity (INL), as discussed in the
Analog Outputs section. For optimum INL performance, the
single-ended, buffered voltage output configuration is suggested.
AD9751
IOUTA
IOUTB
50
25
50
VOUTA = 0V TO 0.5V
IOUTFS = 20mA
Figure 23. 0 V to 0.5 V Unbuffered Voltage Output
SINGLE-ENDED BUFFERED VOLTAGE OUTPUT
Figure 24 shows a buffered single-ended output configuration in
which the op amp performs an I–V conversion on the AD9751
output current. The op amp maintains IOUTA (or IOUTB) at a
virtual ground, thus minimizing the nonlinear output impedance
effect on the DAC’s INL performance as discussed in the
Analog Output section. Although this single-ended configura-
tion typically provides the best dc linearity performance, its ac
distortion performance at higher DAC update rates may be
limited by the op amp’s slewing capabilities. The op amp pro-
vides a negative unipolar output voltage and its full-scale output
voltage is simply the product of RFB and IOUTFS. The full-scale
output should be set within the op amp’s voltage output swing
capabilities by scaling IOUTFS and/or RFB. An improvement in ac
distortion performance may result with a reduced IOUTFS, since
the signal current the op amp will be required to sink will subse-
quently be reduced.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9751ASTZKL1 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9751ASTZRL | 功能描述:IC DAC 10BIT 300MSPS 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD9751-EB | 功能描述:BOARD EVAL FOR AD9751 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9752 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 125 MSPS High Performance TxDAC D/A Converter |
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