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參數(shù)資料
| 型號(hào)： | AD9753-EB |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 3/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9753 |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TxDAC+® |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 300M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 設(shè)置時(shí)間： | 11ns |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9753 |
| 相關(guān)產(chǎn)品： | AD9753ASTZRL-ND - IC DAC 12BIT 300MSPS 48LQFP AD9753ASTZ-ND - IC DAC 12BIT 300MSPS 48-LQFP |
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REV. B
AD9753
–11–
PORT 1
DATA X
DATA Y
tH
tS
tLPW
tPD
DATA X
DATA Y
1/2 CYCLE +
tPD
PORT 2
IOUTA OR IOUTB
CLK
DATA IN
Figure 7a. DAC Input Timing Requirements with
PLL Active, Single Clock Cycle
PORT 1
DATA X
DATA Z
DATA X
DATA Y
PORT 2
IOUTA OR IOUTB
CLK
DATA IN
DATA Z
DATA W
XXX
DATA W
DATA Y
Figure 7b. DAC Input Timing Requirements with
PLL Active, Multiple Clock Cycles
Typically, the VCO can generate outputs of 100 MHz to
400 MHz. The range control is used to keep the VCO operating
within its designed range, while allowing input clocks as low as
6.25 MHz. With the PLL active, logic levels at DIV0 and DIV1
determine the divide (prescaler) ratio of the range controller.
Table I gives the frequency range of the input clock for the
different states of DIV0 and DIV1.
Table I. CLK Rates for DIV0, DIV1 Levels with PLL Active
CLK Frequency
DIV1
DIV0
Range Controller
50 MHz–150 MHz
0
÷1
25 MHz–100 MHz
0
1
÷2
12.5 MHz–50 MHz
1
0
÷4
6.25 MHz–25 MHz
1
÷8
A 392
resistor and 1.0 F capacitor connected in series from
LPF to PLLVDD are required to optimize the phase noise versus
the settling/acquisition time characteristics of the PLL. To
obtain optimum noise and distortion performance, PLLVDD
should be set to a voltage level similar to DVDD and
CLKVDD.
In general, the best phase noise performance for any PLL range
control setting is achieved with the VCO operating near its maxi-
mum output frequency of 400 MHz.
As stated earlier, applications requiring input data rates below
6.25 MSPS must disable the PLL clock multiplier and provide
an external 2
× reference clock. At higher data rates however,
applications already containing a low phase noise (i.e., jitter)
REFERENCE CONTROL AMPLIFIER
The AD9753 also contains an internal control amplifier that is
used to regulate the DAC’s full-scale output current, IOUTFS.
The control amplifier is configured as a voltage-to-current
converter as shown in Figure 4, so that its current output, IREF, is
determined by the ratio of VREFIO and an external resistor, RSET,
as stated in Equation 4. IREF is applied to the segmented current
sources with the proper scaling factor to set IOUTFS, as stated in
Equation 3.
The control amplifier allows a wide (10:1) adjustment span of
IOUTFS over a 2 mA to 20 mA range by setting IREF between
62.5
A and 625 A. The wide adjustment span of I
OUTFS
provides several application benefits. The first benefit relates
directly to the power dissipation of the AD9753, which is
proportional to IOUTFS (refer to the Power Dissipation section).
The second benefit relates to the 20 dB adjustment, which is
useful for system gain control purposes.
The small signal bandwidth of the reference control amplifier is
approximately 500 kHz and can be used for low frequency,
small signal multiplying applications.
PLL CLOCK MULTIPLIER OPERATION
The Phase-Locked Loop (PLL) is intrinsic to the operation of
the AD9753 in that it produces the necessary internally syn-
chronized 2
× clock for the edge-triggered latches, multiplexer,
and DAC.
With PLLVDD connected to its supply voltage, the AD9753 is
in PLL mode. Figure 6 shows a functional block diagram of the
AD9753 clock control circuitry with PLL active. The circuitry
consists of a phase detector, charge pump, voltage controlled
oscillator (VCO), input data rate range control, clock logic
circuitry, and control input/outputs. The
÷2 logic in the feed-
back loop allows the PLL to generate the 2
× clock needed for
the DAC output latch.
CLKCOM
TO INPUT
LATCHES
CLKVDD
(3.0V TO 3.6V)
PLLLOCK
CHARGE
PUMP
PHASE
DETECTOR
LPF
PLLVDD
VCO
392
1.0 F
3.0V TO
3.6V
RANGE
CONTROL
(
1, 2, 4, 8)
DIV0
DIV1
DIFFERENTIAL-
TO-
SINGLE-ENDED
AMP
2
TO DAC
LATCH
CLK+
CLK–
AD9753
Figure 6. Clock Circuitry with PLL Active
Figure 7 defines the input and output timing for the AD9753
with the PLL active. CLK in Figure 7 represents the clock
that is generated external to the AD9753. The input data at
both Ports 1 and 2 is latched on the same CLK rising edge.
CLK may be applied as a single-ended signal by tying CLK– to
midsupply and applying CLK to CLK+, or as a differential
signal applied to CLK+ and CLK–.
RESET has no purpose when using the internal PLL and should
be grounded. When the AD9753 is in PLL mode, PLLLOCK
is the output of the internal phase detector. When locked, the
lock output in this mode will be a Logic 1.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9754 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 125 MSPS High Performance TxDAC D/A Converter |
| AD9754AR | 功能描述:IC DAC 14BIT 125MSPS HP 28-SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類(lèi)型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD9754ARRL | 制造商:Analog Devices 功能描述:DAC 1-CH 14-bit 28-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:14-BIT, 125 MSPS+ TXDAC D/A CONVERTER - Tape and Reel |
| AD9754ARU | 功能描述:IC DAC 14BIT 125MSPS 28-TSSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類(lèi)型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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