參數(shù)資料
型號: AD9760ARU50
廠商: Analog Devices Inc
文件頁數(shù): 12/23頁
文件大?。?/td> 0K
描述: IC DAC 10BIT 50MSPS 28-TSSOP
產(chǎn)品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 50
系列: TxDAC®
設置時間: 35ns
位數(shù): 10
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 175mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 28-TSSOP
包裝: 管件
輸出數(shù)目和類型: 2 電流,單極;2 電流,雙極
采樣率(每秒): 60M
配用: AD9760-EBZ-ND - BOARD EVAL FOR AD9760
DC SPECIFICATIONS
Parameter
Min
Typ
Max
Units
RESOLUTION
10
Bits
DC ACCURACY
1
Integral Linearity Error (INL)
–1.0
±0.5
+1.0
LSB
Differential Nonlinearity (DNL)
–0.5
±0.25
+0.5
LSB
MONOTONICITY
Guaranteed Over Specified Temperature Range
ANALOG OUTPUT
Offset Error
–0.025
+0.025
% of FSR
Gain Error (Without Internal Reference)
–10
±2
+10
% of FSR
Gain Error (With Internal Reference)
–10
±1
+10
% of FSR
Full-Scale Output Current
2
2.0
20.0
mA
Output Compliance Range
–1.0
1.25
V
Output Resistance
100
k
Output Capacitance
5
pF
REFERENCE OUTPUT
Reference Voltage
1.08
1.20
1.32
V
Reference Output Current
3
100
nA
REFERENCE INPUT
Input Compliance Range
0.1
1.25
V
Reference Input Resistance
1
M
Small Signal Bandwidth (w/o CCOMP1)
4
1.4
MHz
TEMPERATURE COEFFICIENTS
Offset Drift
0
ppm of FSR/
°C
Gain Drift (Without Internal Reference)
±50
ppm of FSR/
°C
Gain Drift (With Internal Reference)
±100
ppm of FSR/
°C
Reference Voltage Drift
±50
ppm/
°C
POWER SUPPLY
Supply Voltages
AVDD5
2.7
5.0
5.5
V
DVDD
2.7
5.0
5.5
V
Analog Supply Current (IAVDD)25
30
mA
Digital Supply Current (IDVDD)
6
35
mA
Supply Current Sleep Mode (IAVDD)
8.5
mA
Power Dissipation
6 (5 V, I
OUTFS = 20 mA)
140
175
mW
Power Dissipation7 (5 V, IOUTFS = 20 mA)
190
mW
Power Dissipation
7 (3 V, I
OUTFS = 2 mA)
45
mW
Power Supply Rejection Ratio—AVDD
–0.04
+0.04
% of FSR/V
Power Supply Rejection Ratio—DVDD
–0.025
+0.025
% of FSR/V
OPERATING RANGE
–40
+85
°C
NOTES
1Measured at I
OUTA, driving a virtual ground.
2Nominal full-scale current, I
OUTFS, is 32
× the IREF current.
3Use an external buffer amplifier to drive any external load.
4Reference bandwidth is a function of external cap at COMP1 pin and signal level. Refer to Figure 41.
5For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance.
6Measured at f
CLOCK = 50 MSPS and fOUT = 1.0 MHz.
7Measured as unbuffered voltage output into 50
RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and fOUT = 40 MHz.
Specifications subject to change without notice.
(TMIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted)
–2–
REV. B
AD9760/AD9760-50–SPECIFICATIONS
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