參數(shù)資料
型號(hào): AD9760ARU50
廠商: Analog Devices Inc
文件頁(yè)數(shù): 19/23頁(yè)
文件大小: 0K
描述: IC DAC 10BIT 50MSPS 28-TSSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 50
系列: TxDAC®
設(shè)置時(shí)間: 35ns
位數(shù): 10
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 175mW
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 管件
輸出數(shù)目和類(lèi)型: 2 電流,單極;2 電流,雙極
采樣率(每秒): 60M
配用: AD9760-EBZ-ND - BOARD EVAL FOR AD9760
AD9760
–5–
REV. B
PIN CONFIGURATION
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
28
27
26
25
24
23
22
21
NC = NO CONNECT
(MSB) DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NC
CLOCK
DVDD
DCOM
NC
AVDD
COMP2
IOUTA
IOUTB
ACOM
COMP1
FS ADJ
REFIO
REFLO
SLEEP
TOP VIEW
(Not to Scale)
AD9760
PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Description
1
DB9
Most Significant Data Bit (MSB).
2–9
DB8–DB1
Data Bits 1–8.
10
DB0
Least Significant Data Bit (LSB).
11–14, 25 NC
No Internal Connection.
15
SLEEP
Power-Down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated if
not used.
16
REFLO
Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.
17
REFIO
Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to
AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).
Requires 0.1
F capacitor to ACOM when internal reference activated.
18
FS ADJ
Full-Scale Current Output Adjust.
19
COMP1
Bandwidth/Noise Reduction Node. Add 0.1
F to AVDD for optimum performance.
20
ACOM
Analog Common.
21
IOUTB
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
22
IOUTA
DAC Current Output. Full-scale current when all data bits are 1s.
23
COMP2
Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1
F capacitor.
24
AVDD
Analog Supply Voltage (+2.7 V to +5.5 V).
26
DCOM
Digital Common.
27
DVDD
Digital Supply Voltage (+2.7 V to +5.5 V).
28
CLOCK
Clock Input. Data latched on positive edge of clock.
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