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參數(shù)資料
| 型號： | AD9764-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9764 |
| 產(chǎn)品培訓模塊： | DAC Architectures |
| 標準包裝： | 1 |
| 系列： | TxDAC® |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 設置時間： | 35ns |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9764 |
REV. B
AD9764
–13–
Since the AD9764 is capable of being updated up to 125 MSPS,
the quality of the clock and data input signals are important in
achieving the optimum performance. Operating the AD9764
with reduced logic swings and a corresponding digital supply
(DVDD) will result in the lowest data feedthrough and on-chip
digital noise. The drivers of the digital data interface circuitry
should be specified to meet the minimum setup and hold times
of the AD9764 as well as its required min/max input logic level
thresholds.
Digital signal paths should be kept short and run lengths
matched to avoid propagation delay mismatch. The insertion
of a low value resistor network (i.e., 20
to 100 ) between
the AD9764 digital inputs and driver outputs may be helpful in
reducing any overshooting and ringing at the digital inputs that
contribute to data feedthrough. For longer run lengths and high
data update rates, strip line techniques with proper termination
resistors should be considered to maintain “clean” digital inputs.
The external clock driver circuitry should provide the AD9764
with a low jitter clock input meeting the min/max logic levels
while providing fast edges. Fast clock edges will help minimize
any jitter that will manifest itself as phase noise on a recon-
structed waveform. Thus, the clock input should be driven by
the fastest logic family suitable for the application.
Note, that the clock input could also be driven via a sine wave,
which is centered around the digital threshold (i.e., DVDD/2)
and meets the min/max logic threshold. This will typically result
in a slight degradation in the phase noise, which becomes more
noticeable at higher sampling rates and output frequencies.
Also, at higher sampling rates, the 20% tolerance of the digital
logic threshold should be considered since it will affect the effec-
tive clock duty cycle and, subsequently, cut into the required
data setup and hold times.
SLEEP MODE OPERATION
The AD9764 has a power-down function that turns off the
output current and reduces the supply current to less than
8.5 mA over the specified supply range of 2.7 V to 5.5 V and
temperature range. This mode can be activated by applying a
logic level “1” to the SLEEP pin. This digital input also con-
tains an active pull-down circuit that ensures the AD9764 re-
mains enabled if this input is left disconnected. The SLEEP
input with active pull-down requires <40
A of drive current.
The power-up and power-down characteristics of the AD9764
are dependent upon the value of the compensation capacitor
connected to COMP1. With a nominal value of 0.1
F, the
AD9764 takes less than 5
s to power down and approximately
3.25 ms to power back up. Note, the SLEEP MODE should not
be used when the external control amplifier is used as shown in
Figure 27.
POWER DISSIPATION
The power dissipation, PD, of the AD9764 is dependent on
several factors, including: (1) AVDD and DVDD, the power
supply voltages; (2) IOUTFS, the full-scale current output; (3)
fCLOCK, the update rate; and (4) the reconstructed digital input
waveform. The power dissipation is directly proportional to the
analog supply current, IAVDD, and the digital supply current,
IDVDD. IAVDD is directly proportional to IOUTFS, as shown in
Figure 30, and is insensitive to fCLOCK.
IOUTFS – mA
30
0
220
4
6
8
10
1214
1618
25
20
15
10
5
I AVDD
–
mA
Figure 30. IAVDD vs. IOUTFS
Conversely, IDVDD is dependent on both the digital input wave-
form, fCLOCK, and digital supply DVDD. Figures 31 and 32
show IDVDD as a function of full-scale sine wave output ratios
(fOUT/fCLOCK) for various update rates with DVDD = 5 V and
DVDD = 3 V, respectively. Note, how IDVDD is reduced by more
than a factor of 2 when DVDD is reduced from 5 V to 3 V.
RATIO – fOUT/fCLK
18
16
0
0.01
1
0.1
I DVDD
–
mA
8
6
4
2
12
10
14
5MSPS
25MSPS
50MSPS
100MSPS
125MSPS
Figure 31. IDVDD vs. Ratio @ DVDD = 5 V
RATIO – fOUT/fCLK
8
0
0.01
1
0.1
I DVDD
–
mA
6
4
2
5MSPS
25MSPS
50MSPS
100MSPS
125MSPS
Figure 32. IDVDD vs. Ratio @ DVDD = 3 V
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