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參數(shù)資料
型號(hào): AD9765ASTZRL
廠商: Analog Devices Inc
文件頁數(shù): 7/44頁
文件大?。?/td> 0K
描述: IC DAC 12BIT DUAL 125MSPS 48LQFP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 2,000
系列: TxDAC+®
設(shè)置時(shí)間: 35ns
位數(shù): 12
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
功率耗散(最大): 450mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 4 電流,單極;4 電流,雙極
采樣率(每秒): 125M
配用: AD9765-EBZ-ND - BOARD EVAL FOR AD9765
Data Sheet
AD9763/AD9765/AD9767
Rev. G | Page 15 of 44
90
85
80
75
70
65
60
–20
0
–5
–10
–15
S
F
DR
(
d
Bc)
AOUT (dBFS)
0.91MHz/10MSPS
5.91MHz/65MSPS
2.27MHz/25MSPS
11.37MHz/125MSPS
00
61
7-
0
29
Figure 29. Single-Tone SFDR vs. AOUT @ fOUT = fCLK/11
90
85
80
75
70
65
55
60
–20
0
–5
–10
–15
S
F
DR
(
d
Bc)
AOUT (dBFS)
1MHz/5MSPS
2MHz/10MSPS
5MHz/25MSPS
13MHz/65MSPS
25MHz/125MSPS
00
61
7-
0
30
Figure 30. Single-Tone SFDR vs. AOUT @ fOUT = fCLK/5
80
75
70
65
55
60
–20
0
–5
–10
–15
S
F
DR
(
d
B
c)
AOUT (dBFS)
3.38MHz/3.36MHz@25MSPS
0.965MHz/1.035MHz@7MSPS
6.75MHz/7.25MHz@65MSPS
16.9MHz/18.1MHz@125MSPS
00
61
7-
0
31
Figure 31. Dual-Tone SFDR vs. AOUT @ fOUT = fCLK/7
75
70
65
60
55
20
140
120
100
80
60
40
S
INA
D
(
d
Bc)
fCLK (MSPS)
IOUTFS = 20mA
IOUTFS = 10mA
IOUTFS = 5mA
0
06
17
-0
32
Figure 32. SINAD vs. fCLK and IOUTFS @ fOUT = 5 MHz and 0 dBFS
0.6
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0
4000
1000
2000
3000
IN
L
(
L
S
B
)
CODE
00
61
7-
03
3
Figure 33. Typical INL
0.05
–0.35
–0.30
–0.25
–0.20
–0.15
–0.10
–0.05
0
4000
3500
3000
2500
2000
1500
1000
500
DN
L
(
L
S
B
)
CODE
00
61
7-
03
4
Figure 34. Typical DNL
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