參數(shù)資料
型號(hào)： AD9767ASTZ
廠商： Analog Devices Inc
文件頁數(shù)： 14/44頁
文件大?。?/td> 0K
描述： IC DAC 14BIT DUAL 125MSPS 48LQFP
產(chǎn)品培訓(xùn)模塊： DAC Architectures
標(biāo)準(zhǔn)包裝： 1
系列： TxDAC+®
設(shè)置時(shí)間： 35ns
位數(shù)： 14
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 450mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤
輸出數(shù)目和類型： 4 電流，單極；4 電流，雙極
采樣率（每秒）： 125M
產(chǎn)品目錄頁面： 785 (CN2011-ZH PDF)
配用： AD9767-EBZ-ND - BOARD EVAL FOR AD9767
Data Sheet
AD9763/AD9765/AD9767
Rev. G | Page 21 of 44
THEORY OF OPERATION
5V
CLK1/IQCLK CLK2/IQRESET
AVDD
FSADJ1
REFIO
FSADJ2
1.2V REF
CHANNEL 1 LATCH
CHANNEL 2 LATCH
MODE
MULTIPLEXING LOGIC
5V
GAINCTRL
ACOM
SLEEP
AD9763/
AD9765/
AD9767
RSET1
2k
0.1F
RSET2
2k
CLK
DIVIDER
DAC1
LATCH
PMOS
CURRENT
SOURCE
ARRAY
PMOS
CURRENT
SOURCE
ARRAY
WRT1/
IQWRT
RETIMED CLOCK OUTPUT*
LECROY 9210
PULSE
GENERATOR
50
DIGITAL
DATA
TEKTRONIX
AWG2021
w/OPTION 4
WRT2/
IQSEL
*AWG2021 CLOCK RETIMED SUCH THAT
DIGITAL DATA TRANSITIONS ON FALLING
EDGE OF 50% DUTY CYCLE CLOCK.
PORT 1
PORT 2
IOUTA1
IOUTB1
IOUTA2
IOUTB2
DAC2
LATCH
LSB
SWITCH
SEGMENTED
SWITCHES FOR
DAC2
SEGMENTED
SWITCHES FOR
DAC1
LSB
SWITCH
TO HP3589A
OR EQUIVALENT
SPECTRUM/
NETWORK
ANALYZER
Mini-Circuits
T1-1T
50
00
61
7-
0
57
DVDD1/
DVDD2
DCOM1/
DCOM2
DVDD1/DVDD2
DCOM1/DCOM2
Figure 57. Basic AC Characterization Test Setup for AD9763/AD9765/AD9767,
Testing Port 1 in Dual-Port Mode, Using Independent GAINCTRL Resistors on FSADJ1 and FSADJ2
0.1F
5V
CLK1/IQCLK
CLK2/IQRESET
AVDD
FSADJ1
REFIO
FSADJ2
1.2V REF
CHANNEL 1 LATCH
CHANNEL 2 LATCH
MODE
MULTIPLEXING LOGIC
5V
GAINCTRL
SLEEP
ACOM
DIGITAL DATA INPUTS
NOTES
1. IN THIS CONFIGURATION, THE 22nF CAPACITOR AND 256 RESISTOR ARE NOT REQUIRED BECAUSE RSET = 2k.
RSET1
2k
IREF1
RSET2
2k
IREF2
WRT1/
IQWRT
WRT2/
IQSEL
IOUTB2
IOUTA2
IOUTB1
IOUTA1
PMOS
CURRENT
SOURCE
ARRAY
PMOS
CURRENT
SOURCE
ARRAY
CLK
DIVIDER
DAC1
LATCH
DAC2
LATCH
SEGMENTED
SWITCHES FOR
DAC1
LSB
SWITCH
SEGMENTED
SWITCHES FOR
DAC2
LSB
SWITCH
VDIFF = VOUTA – VOUTB
VOUT1A
VOUT1B
VOUT2A
VOUT2B
RL1A
50
RL1B
50
RL2A
50
RL2B
50
00
61
7-
0
58
PORT 1
PORT 2
DVDD1/
DVDD2
DCOM1/
DCOM2
AD9763/
AD9765/
AD9767
Figure 58. Simplified Block Diagram
FUNCTIONAL DESCRIPTION
Figure 58 shows a simplified block diagram of the AD9763/
AD9765/AD9767. The AD9763/AD9765/AD9767 consist of
two DACs, each one with its own independent digital control
logic and full-scale output current control. Each DAC contains
a PMOS current source array capable of providing up to 20 mA
of full-scale current (IOUTFS).
The array is divided into 31 equal currents that make up the five
most significant bits (MSBs). The next four bits, or middle bits,
consist of 15 equal current sources whose value is 1/16th of an
MSB current source. The remaining LSB is a binary weighted
fraction of the middle bit current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances the dynamic performance for multitone or low
amplitude signals and helps maintain the high output impedance
of each DAC (that is, >100 kΩ).
All of these current sources are switched to one of the two
output nodes (that is, IOUTA or IOUTB) via the PMOS differential
current switches. The switches are based on a new architecture
that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching complementary drive signals to the inputs of the
differential current switches.
The analog and digital sections of the AD9763/AD9765/AD9767
have separate power supply inputs (that is, AVDD and DVDD1/
DVDD2) that can operate independently at 3.3 V or 5 V. The
digital section, which is capable of operating up to a 125 MSPS
clock rate, consists of edge-triggered latches and segment decoding
logic circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.20 V band gap
voltage reference, and two reference control amplifiers.
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