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參數(shù)資料
| 型號： | AD976AARZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 200KSPS 28SOIC |
| 標準包裝： | 1,000 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 100mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 28-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，雙極 |
AD976/AD976A
–14–
REV. C
8051 Interface
Figure 21 illustrates the use of the AD976/AD976A with an
8051 microcontroller.
DB7
DB0
BYTE
A0
CS
BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
BUSY
AD976/
AD976A
8051
LATCH
BUS
AD0
AD7
P0
A15
A8
P2
RD
WR
INT
R/
C
ADDR
DECODE
Figure 21. AD976/AD976A to 8051 Interface
TMS320C25 Interface
Figure 22 shows an interface between the AD976/AD976A and
the TMS320C25.
TIMER
ADDRESS BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
DATA BUS
DB15
DB0
BUSY
AD976/
AD976A
R/
C
EN
ADDR
DECODE
A0
A15
D15
D0
TMS320C25
R/W
IS
READY
STRB
NSC
INT
CS
Figure 22. AD976/AD976A to TMS320C25 Interface
ADSP-2111 Interface
Figure 23 shows an interface to the ADSP-2111 signal processor.
In this example, CS is being used to control conversions and is
generated by an external timer. A conversion is initiated each
time the timer output goes low as long as you are not reading
from the AD976/AD976A and while the Flag Output (FO) pin
of the ADSP-2111 is low. When a conversion is complete, the
BUSY line will return high. With the IRQn pin programmed to
generate an interrupt on a high-to-low transition, an interrupt
will occur at the end of each conversion. The 16-bit result of the
conversion can be read from within the interrupt service routine
by first forcing FO high, then performing a read operation with
the AD976/AD976A.
ADDRESS BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
DATA BUS
DB15
DB0
BUSY
AD976/
AD976A
EN
ADDR
DECODE
A0
A13
D15
D0
ADSP-2111
DMS
IRQn
CS
TIMER
RD
FO
R/
C
Figure 23. AD976/AD976A to ADSP-2111 Interface
POWER SUPPLIES AND DECOUPLING
The AD976/AD976A has two power supply input pins. VANA
and VDIG provide the supply voltages to the analog and digital
portions, respectively. VANA is the +5 V supply for the on-chip
analog circuitry, and VDIG is the +5 V supply for the on-chip
digital circuitry. The AD976/AD976A is designed to be inde-
pendent of power supply sequencing and, thus, free from supply
voltage induced latch-up.
With high performance linear circuits, changes in the power
supplies can result in undesired circuit performance. Optimally,
well regulated power supplies should be chosen with less than
1% ripple. The ac output impedance of a power supply is a
complex function of frequency and it will generally increase with
frequency. Thus, high frequency switching, such as that encoun-
tered with digital circuitry, requires the fast transient currents
that most power supplies can not adequately provide. Such a
situation results in large voltage spikes on the supplies. To com-
pensate for the finite ac output impedance of most supplies,
charge “reserves” should be stored in bypass capacitors. This
will effectively lower the supplies impedance presented to the
AD976/AD976A VANA and VDIG pins and reduce the magnitude
of these spikes. Decoupling capacitors, typically 0.1
F, should
be placed close to the power supply pins of the AD976/AD976A
to minimize any inductance between the capacitors and the
VANA and VDIG pins.
The AD976/AD976A may be operated from a single +5 V sup-
ply. When separate supplies are used, however, it is beneficial to
have larger capacitors, 10
F, placed between the logic supply
(VDIG) and digital common (DGND) and between the analog
supply (VANA) and the analog common (AGND2). Additionally,
10
F capacitors should be located in the vicinity of the ADC to
further reduce low frequency ripple. In systems where the device
will be subjected to harsh environmental noise, additional de-
coupling may be required.
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