- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17103 > AD9785-DPG2-EBZ (Analog Devices Inc)BOARD EVALUATION FOR AD9785 PDF資料下載
參數(shù)資料
| 型號： | AD9785-DPG2-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/64頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9785 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TxDAC® |
| DAC 的數(shù)量： | 2 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 800M |
| 數(shù)據(jù)接口： | 串行 |
| 設(shè)置時間： | 22ms |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板，纜線，CD |
| 已用 IC / 零件： | AD9785 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
AD9785/AD9787/AD9788
Rev. A | Page 23 of 64
Instruction Byte
The instruction byte contains the following information as
shown in the instruction byte bit map.
Instruction Byte Information Bit Map
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
R/W
X
A4
A3
A2
A1
A0
R/W—Bit 7 of the instruction byte determines whether a read
or write data transfer occurs after the instruction byte write.
Logic 1 indicates a read operation. Logic 0 indicates a write
operation.
X, X —Bit 6 and Bit 5 of the instruction byte are don’t care. In
previous TxDACs, such as the AD9779, these bits define the
number of registers written to or read from in an SPI read/write
operation. In the AD9785/AD9787/AD9788, the register itself
now defines how many bytes are written to or read from.
instruction byte determine which register is accessed during the
data transfer portion of the communication cycle.
Serial Interface Port Pin Description
SCLK—Serial Clock
The serial clock pin is used to synchronize data to and from the
AD9785/AD9787/AD9788 and to run the internal state machines.
SCLK maximum frequency is 40 MHz.
SPI_CSB—Chip Select
Active low input that allows more than one device on the same
serial communications line. The SPI_SDO and SPI_SDIO pins
go to a high impedance state when this input is high. If driven
high during any communication cycle, that cycle is suspended
until SPI_CSB is reactivated low. Chip select can be tied low in
systems that maintain control of SCLK.
SPI_SDIO—Serial Data I/O
Data is always written into the AD9785/AD9787/AD9788 on
this pin. However, this pin can be used as a bidirectional data
line. Bit 7 of Register 0x00 controls the configuration of this pin.
The default is Logic 0, which configures the SPI_SDIO pin for
input only (4-wire) operation.
SPI_SDO—Serial Data Output
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. In the case where the
AD9785/AD9787/AD9788 operate in a single bidirectional
I/O mode, this pin does not output data and is set to a high
impedance state.
MSB/LSB Transfers
The AD9785/AD9787/AD9788 serial port can support both
most significant bit (MSB) first or least significant bit (LSB)
first data formats. This functionality is controlled by Bit 6 of the
communication (COMM) register. The default value of COMM
Register Bit 6 is low (MSB first). When COMM Register Bit 6 is
set high, the serial port is in LSB first format. The instruction byte
must be written in the format indicated by COMM Register Bit 6.
That is, if the device is in LSB first mode, the instruction byte
must be written from least significant bit to most significant bit.
For MSB first operation, the serial port controller generates the
most significant byte (of the specified register) address first,
followed by the next lesser significant byte addresses until the
I/O operation is complete. All data written to or read from the
AD9785/AD9787/AD9788 must be in MSB first order.
If the LSB mode is active, the serial port controller generates the
least significant byte address first, followed by the next greater
significant byte addresses until the I/O operation is complete.
All data written to or read from the AD9785/AD9787/AD9788
must be in LSB first order.
SPI Resynchronization Capability
If the SPI port becomes unsynchronized at any time, toggling
SCLK for eight or more cycles with SPI_CSB held high resets
the SPI port state machine. The device is then ready for the next
register read or write access.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EEM36DTMD-S189 | CONN EDGECARD 72POS R/A .156 SLD |
| EEM36DTMH-S189 | CONN EDGECARD 72POS R/A .156 SLD |
| 0210390421 | CABLE FLAT FLEX 1.18" 1MM 26POS |
| EVAL-AD5791SDZ | BOARD EVAL FOR AD5791 |
| VE-J2R-EZ | CONVERTER MOD DC/DC 7.5V 25W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9785-EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD9785 制造商:Analog Devices 功能描述:DUAL 12B, 1GSPS D-A CONVERTER - Bulk 制造商:Analog Devices 功能描述:Digital to Analog Eval. Board |
| AD9786 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2】/4】/8】 Interpolation and Signal Processing |
| AD9786BSV | 制造商:Analog Devices 功能描述:DAC 1-CH Interpolation Filter 16-bit 80-Pin TQFP EP 制造商:Analog Devices 功能描述:IC 16BIT DAC SMD 9786 TQFP80 |
| AD9786BSVRL | 制造商:Analog Devices 功能描述:DAC 1-CH Interpolation Filter 16-bit 80-Pin TQFP EP T/R |
| AD9786BSVZ | 功能描述:IC DAC 16BIT INTERPOL/SP 80TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。