參數(shù)資料
型號(hào)： AD9849AKSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 14/32頁(yè)
文件大?。?/td> 0K
描述： IC CCD SIGNAL PROC 12BIT 48LQFP
標(biāo)準(zhǔn)包裝： 1
類型： CCD 信號(hào)處理器，12 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤
REV. A
–21–
AD9848/AD9849
H2 = H4 = high during the blanking, as shown in Figure 11.
Up to four individual sequences are available for HBLK.
Horizontal Sequence Control
The AD9848/AD9849 uses Sequence Change Positions (SCP)
and Sequence Pointers (SPTR) to organize the individual
horizontal sequences. Up to four SCPs are available to divide
the readout into four separate regions, as shown in Figure 12.
The SCP 0 is always hard-coded to line 0, and SCP1–3 are
register programmable. During each region bounded by the
SCP, the SPTR registers designate which sequence is used by
each signal. CLPOB, CLPDM, PBLK, and HBLK each have a
separate set of SCP. For example, CLPOBSCP1 will define Region
0 for CLPOB, and in that region any of the four individual
CLPOB sequences may be selected with the CLPOBSPTR
registers. The next SCP defines a new region and in that region
each signal can be assigned to a different individual sequence. The
Sequence Control Registers are summarized in Table VI.
(3)
(2)
(1)
HD
CLPOB
CLPDM
PBLK
. . .
NOTES
PROGRAMMABLE SETTINGS:
(1) START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW)
(2) FIRST TOGGLE POSITION
(3) SECOND TOGGLE POSITION
. . .
CLAMP
Figure 9. Clamp and Preblank Pulse Placement
(2)
(1)
HD
HBLK
. . .
NOTES
PROGRAMMABLE SETTINGS:
(1) FIRST TOGGLE POSITION = START OF BLANKING
(2) SECOND TOGGLE POSITION = END OF BLANKING
. . .
BLANK
Figure 10. Horizontal Blanking (HBLK) Pulse Placement
HD
HBLK
. . .
THE POLARITY OF H1 DURING BLANKING IS PROGRAMMABLE (H2 IS OPPOSITE POLARITY OF H1)
. . .
H1/H3
H2/H4
. . .
Figure 11. HBLK Masking Control
Individual CLPOB, CLPDM, PBLK Sequences
The AFE horizontal timing consists of CLPOB, CLPDM, and
PBLK, as shown in Figure 9. These three signals are indepen-
dently programmed using the registers in Table IV. SPOL is the
start polarity for the signal, and TOG1 and TOG2 are the first
and second toggle positions of the pulse. All three signals are
active low and should be programmed accordingly. Up to four
individual sequences can be created for each signal.
Individual HBLK Sequences
The HBLK programmable timing shown in Figure 10 is similar to
CLPOB, CLPDM, and PBLK. However, there is no start polar-
ity control. Only the toggle positions are used to designate the
start and the stop positions of the blanking period. Additionally,
there is a polarity control HBLKMASK that designates the
polarity of the horizontal clock signals H1–H4 during the blank-
ing period. Setting HBLKMASK high will set H1 = H3 = low and
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