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參數(shù)資料
| 型號： | AD9878BST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Mixed-Signal Front End for Broadband Applications |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | MS-026BED, LQFP-100 |
| 文件頁數(shù)： | 19/36頁 |
| 文件大?。?/td> | 749K |
| 代理商： | AD9878BST |
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AD9878
MSB/LSB TRANSFERS
The AD9878 serial port can support either MSB-first or LSB-first
data formats. This functionality is controlled by the LSB-first bit
in Register 0x00.
Rev. A | Page 19 of 36
The AD9878 default serial port mode is MSB-first (see Figure 21),
which is programmed by setting Register 0x00 low. In MSB-first
mode, the instruction byte and data bytes must be written from
the MSB to the LSB. In MSB-first mode, the serial port internal
byte address generator decrements for each byte of the multibyte
communication cycle. When decrementing from 0x00, the
address generator changes to 0x1F.
When the LSB-first bit in Register 0x00 is set active high, the
AD9878 serial port is in LSB-first format (Figure 22). In LSB-
first mode, the instruction byte and data bytes must be written
from the LSB to the MSB. In LSB-first mode, the serial port
internal byte address generator increments for each byte of the
multibyte communication cycle. When incrementing from
0x1F, the address generator changes to 0x00.
CS
R/W
N1
N0
A4
A3
A2
A1
A0 D7nD6n
D20D10D00
D7nD6n
D20D10D00
SCLK
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SDIO
SDO
0
Figure 21. Serial Register Interface Timing, MSB-First Mode
D00D10D20
D6nD7n
SCLK
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SDIO
SDO
CS
A0
A1
A2
A3
A4
N0
N1 R/W D00D10D20
D6nD7n
0
Figure 22. Serial Register Interface Timing, LSB-First Mode
NOTES ON SERIAL PORT OPERATION
The AD9878 serial port configuration bits reside in Bit 6 and
Bit 7 of Register Address 0x00. Note that the configuration
changes immediately upon writing to the last bit of the register.
For multibyte transfers, writing to this register might occur
during a communication cycle. Measures must be taken to
compensate for this new configuration for the remaining bytes of
the current communication cycle.
The same considerations apply when setting the reset bit in
Register Address 0x00. All other registers are set to their default
values, but the software reset does not affect the bits in Register
Address 0x00. It is recommended to use only single-byte transfers
when changing serial port configurations or initiating a software
reset. A write to Bit 1, Bit 2, and Bit 3 of Address 0x00 with the
same logic levels as Bit 7, Bit 6, and Bit 5 (bit pattern: XY1001YX
binary) allows the user to reprogram a lost serial port config-
uration and to reset the registers to their default values. A
second write to Address 0x00, with the reset bit low and the
serial port configuration as specified above (XY), reprograms
the OSCIN multiplier setting. A changed f
SYSCLK
frequency is
stable after a maximum of 200 f
MCLK
cycles (wake-up time).
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| AD9878BSTRL | 制造商:Analog Devices 功能描述:Mixed Signal Front End 100-Pin LQFP T/R 制造商:Analog Devices 功能描述:MIXED SGNL FRONT END 100LQFP - Tape and Reel |
| AD9878BSTZ | 功能描述:IC FRONT-END MIXED-SGNL 100-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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