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參數(shù)資料
| 型號： | AD9887AKSZ-170 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/40頁 |
| 文件大小： | 0K |
| 描述： | IC INTRFACE ANALOG/DVI 160-MQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 應(yīng)用： | 圖形卡，VGA 接口 |
| 接口： | 模擬和數(shù)字 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-MQFP（28x28） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 788 (CN2011-ZH PDF) |
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REV. 0
–16–
AD9887
Table V. VCO Frequency Ranges
Pixel Clock
KVCO Gain
PV1
PV0
Range (MHz)
(MHz/V)
0
12–35
150
0
1
35–70
150
1
0
70–110
150
1
110–140
180
Table VI. Charge Pump Current/Control Bits
Ip2
Ip1
Ip0
Current ( A)
00
0
50
0
1
100
0
1
0
150
0
1
250
1
0
350
1
0
1
500
1
0
750
1
1500
3. The 3-Bit Charge Pump Current Register. This register
allows the current that drives the low pass loop lter to be
varied. The possible current values are listed in Table VI.
provides 32 phase-shift steps of 11.25
° each. The Hsync
signal with an identical phase shift is available through the
HSOUT pin. Phase adjustment is still available if the pixel
clock is being provided externally.
4. The 5-Bit Phase Adjust Register. The phase of the generated
sampling clock may be shifted to locate an optimum sam-
pling point within a clock cycle. The Phase Adjust register
The COAST allows the PLL to continue to run at the same
frequency, in the absence of the incoming Hsync signal. This
may be used during the vertical sync period, or any other
time that the Hsync signal is unavailable. The polarity of
the COAST signal may be set through the Coast Polarity Bit.
Also, the polarity of the Hsync signal may be set through the
HSYNC polarity Bit. If not using automatic polarity
detection, the HSYNC and COAST polarity bits should
be set to match the Polarity of their respective signals.
Table VII. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats
Horizontal
Refresh
Frequency
Pixel Rate
Standard
Resolution
Rate (Hz)
(kHz)
(MHz)
VCORNGE
CURRENT
VGA
640
× 480
60
31.5
25.175
00
101
72
37.7
31.500
00
101
75
37.5
31.500
00
110
85
43.3
36.000
00
110
SVGA
800
× 600
56
35.1
36.000
00
101
60
37.9
40.000
01
101
72
48.1
50.000
01
101
75
46.9
49.500
01
101
85
53.7
56.250
01
110
XGA
1024
× 768
60
48.4
65.000
01
110
70
56.5
75.000
10
101
75
60.0
78.750
10
101
80
64.0
85.500
10
101
85
68.3
94.500
10
101
SXGA
1280
× 1024
60
64.0
108.000
10
110
75
80.0
135.000
11
110
85
91.1
157.500
*
10
110
UXGA
1600
× 1200
60
75.0
162.000
*
10
110
65
81.3
175.500
*
10
110
70
87.5
189.000
*
10
110
75
93.8
202.500
*
10
110
85
106.3
229.500
*
11
110
*Graphics sampled at one-half the incoming pixel rate using Alternate Pixel Sampling mode.
OBSOLETE
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9887AKSZ-170 | 制造商:Analog Devices 功能描述:IC DUAL DISPLAY INTERFACE |
| AD9887AKSZ-1701 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887APCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9887KS-100 | 制造商:Analog Devices 功能描述:Interface for Flat Panel Display 160-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:DUAL A/D INTERFACE FOR FLAT PANEL - Bulk |
| AD9887KS-140 | 制造商:Analog Devices 功能描述:Interface for Flat Panel Display 160-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:DUAL A/D INTERFACE FOR FLAT PANEL - Bulk 制造商:Analog Devices 功能描述:IC INTERFACE DUAL DISPLAY |
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