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參數(shù)資料
| 型號： | AD9887AKSZ-170 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTRFACE ANALOG/DVI 160-MQFP |
| 標準包裝： | 24 |
| 應(yīng)用： | 圖形卡，VGA 接口 |
| 接口： | 模擬和數(shù)字 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-MQFP（28x28） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 788 (CN2011-ZH PDF) |
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REV. 0
AD9887
–17–
ADC
DAC
7
8
OFFSET
GAIN
REF
x1.2
IN
CLAMP
VOFF
8
Figure 8. ADC Block Diagram (Single Channel Output)
1V
INPUT
RANGE
VOFF
(128 CODES)
INPUT
RANGE
0.5V
VOFF
(128 CODES)
OFFSET
RANGE
0V
OFFSET
RANGE
Figure 9. Relationship of Offset Range to Input Range
SCAN Function
The SCAN function is intended as a pseudo JTAG function for
manufacturing test of the board. The ordinary operation of the
AD9887 is disabled during SCAN.
To enable the SCAN function, set register 14h, bit 2 to 1. To
SCAN in data to all 48 digital outputs, apply 48 serial bits of
data and 48 clocks (typically 5 MHz, max of 20 MHz) to the
SCANIN and SCANCLK pins respectively. The data is shifted
in on the rising edge of SCANCLK. The first serial bit shifted
in will appear at the RED A<7> output after one clock cycle.
After 48 clocks, the first bit is shifted all the way to the BLU
B<0>. The 48th bit will now be at the RED A<7> output. If
SCANCLK continues after 48 cycles, the data will continue to be
shifted from RED A<7> to BLU B<0> and will come out of the
SCANOUT pin as serial data on the falling edge of SCANCLK.
This is illustrated in Figure 10. A setup time (tSU) of 3 ns
should be plenty and no hold time (tHOLD) is required (
≥ 0 ns).
This is illustrated in Figure 11.
tSU = 3ns
tHOLD = 0ns
SCANCLK
SCANIN
Figure 11. SCAN Setup and Hold
Alternate Pixel Sampling Mode
A Logic 1 input on Clock Invert (CKINV, Pin 94) inverts the
nominal ADC clock. CKINV can be switched between frames
to implement the alternate pixel sampling mode. This allows
higher effective image resolution to be achieved at lower pixel
rates but with lower frame rates.
On one frame, only even pixels are digitized. On the subsequent
frame, odd pixels are sampled. By reconstructing the entire
frame in the graphics controller, a complete image can be recon-
structed. This is very similar to the interlacing process that is
employed in broadcast television systems, but the interlacing is
vertical instead of horizontal. The frame data is still presented to
the display at the full desired refresh rate (usually 60 Hz) so no
flicker artifacts are added.
OEOEOEOEOEOE
Figure 12. Odd and Even Pixels in a Frame
O 1
Figure 13. Odd Pixels from Frame 1
X
BIT 1
BIT 2
X
BIT 1
BIT 2
BIT 47
BIT 48
X
BIT 46
BIT 47
BIT 48
X
SCANCLK
RED A<7>
BLUE B<0>
SCANOUT
SCANIN
BIT 1
BIT 2
BIT 3
BIT 1
BIT 2
BIT 3
XX
X
Figure 10. SCAN Timing
OBSOLETE
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9887AKSZ-170 | 制造商:Analog Devices 功能描述:IC DUAL DISPLAY INTERFACE |
| AD9887AKSZ-1701 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887APCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9887KS-100 | 制造商:Analog Devices 功能描述:Interface for Flat Panel Display 160-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:DUAL A/D INTERFACE FOR FLAT PANEL - Bulk |
| AD9887KS-140 | 制造商:Analog Devices 功能描述:Interface for Flat Panel Display 160-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:DUAL A/D INTERFACE FOR FLAT PANEL - Bulk 制造商:Analog Devices 功能描述:IC INTERFACE DUAL DISPLAY |
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