參數(shù)資料
型號(hào)： AD9944KCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/20頁(yè)
文件大?。?/td> 0K
描述： IC CCD SIGNAL PROCESSOR 32-LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： CCD 信號(hào)處理器，12 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 托盤(pán)
AD9943/AD9944
Data Sheet
Figure 18. AD9944 Recommended Circuit Configuration for CCD Mode
INTERNAL POWER-ON RESET CIRCUITRY
After power-on, the AD9943/AD9944 automatically reset all
internal registers and perform internal calibration procedures.
This takes approximately 1 ms to complete. During this time,
normal clock signals and serial write operations may occur.
However, serial register writes are ignored until the internal
reset operation is completed.
GROUNDING AND DECOUPLING
RECOMMENDATIONS
As shown in Figure 17 and Figure 18, a single ground plane is
recommended for the AD9943/AD9944. This ground plane
should be as continuous as possible. This ensures that all analog
decoupling capacitors provide the lowest possible impedance
path between the power and bypass pins and their respective
ground pins. All decoupling capacitors should be located as
close as possible to the package pins. A single clean power
supply is recommended for the AD9943 and AD9944, but a
separate digital driver supply may be used for DRVDD (Pin 11).
DRVDD should always be decoupled to DRVSS (Pin 12), which
should be connected to the analog ground plane. Advantages of
using a separate digital driver supply include using a lower
voltage (2.7 V) to match levels with a 2.7 V ASIC, and reducing
digital power dissipation and potential noise coupling. If the
digital outputs must drive a load larger than 20 pF, buffering
is the recommended method to reduce digital code transition
noise. Alternatively, placing series resistors close to the digital
output pins may also help reduce noise.
Note: The exposed pad on the bottom of the AD9943/AD9944
should be soldered to the GND plane of the printed circuit board.
24
REFB
23
REFT
22
CCDIN
21
AVSS
D2
1
D3
2
D0
D1
D4
3
20
AVDD
19
SHD
18
SHP
17
CLPOB
D5
4
D6
5
D7
6
D8
7
D9
8
DATA
OUTPUTS
12
D10
D11
9
10
3V
DRIVER
SUPPLY
3V
ANALOG
SUPPLY
3V
ANALOG
SUPPLY
DRV
DD
DRV
S
DV
DD
DAT
ACL
K
D
VSS
P
BL
K
12 13 14 15 16
5
CLOCK
INPUTS
3
SERIAL
INTERFACE
CCDIN
1.0F
0.1F
NC = NO CONNECT
32 31 30 29 28 27 26 25
NC
S
CK
S
DT
A
SL
11
02905-
019
AD9944
TOP VIEW
(Not to Scale)
Rev. C | Page 18 of 20
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