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參數(shù)資料
| 型號： | AD9959/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/44頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9959 |
| 產(chǎn)品培訓模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設計資源： | Phase Coherent FSK Modulator (CN0186) AD9958/59 Eval Brd Schematics AD9958/59 Eval Brd Gerber Files AD9959 Eval Brd BOM |
| 標準包裝： | 1 |
| 主要目的： | 計時，直接數(shù)字合成（DDS） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9959 |
| 主要屬性： | 10 位數(shù)模轉(zhuǎn)換器，32 位調(diào)節(jié)字寬 |
| 次要屬性： | 4 通道 |
| 已供物品： | 板，線纜，軟件 |
| 其它名稱： | AD9959/PCB AD9959/PCB-ND Q2548077 |
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AD9959
Rev. B | Page 19 of 44
MODES OF OPERATION
There are many combinations of modes (for example, single-
tone, modulation, linear sweep) that the AD9959 can perform
simultaneously. However, some modes require multiple data
pins, which can impose limitations. The following guidelines
can help determine if a specific combination of modes can be
performed simultaneously by the AD9959.
CHANNEL CONSTRAINT GUIDELINES
Single-tone mode, two-level modulation mode, and linear
sweep mode can be enabled on any channel and in any
combination at the same time.
Any one or two channels in any combination can perform
four-level modulation. The remaining channels can be in
single-tone mode.
Any channel can perform eight-level modulation. The
three remaining channels can be in single-tone mode.
Any channel can perform 16-level direct modulation. The
three remaining channels can be in single-tone mode.
The RU/RD function can be used on all four channels in
single-tone mode. See the Output Amplitude Control
Mode section for the RU/RD function.
When Profile Pin P2 and Profile Pin P3 are used for RU/RD,
any two channels can perform two-level modulation with
RU/RD or any two channels can perform linear frequency
or phase sweep with RU/RD. The other two channels can
be in single-tone mode.
When Profile Pin P3 is used for RU/RD, any channel can
be used in eight-level modulation with RU/RD. The other
three channels can be in single-tone mode.
When the SDIO_1, SDIO_2, and SDIO_3 pins are used for
RU/RD, any one or two channels, any three channels, or
all four channels can perform two-level modulation with
RU/RD. Any channels not in the two-level modulation can
be in single-tone mode.
When the SDIO_1, SDIO_2, and SDIO_3 pins are used for
RU/RD, any one or two channels can perform four-level
modulation with RU/RD. Any channels not in four-level
modulation can be in single-tone mode.
When the SDIO_1, SDIO_2, and SDIO_3 pins are used for
RU/RD, any channel can perform 16-level modulation with
RU/RD. The other three channels can be in single-tone mode.
Amplitude modulation, linear amplitude sweep modes,
and the RU/RD function cannot operate simultaneously,
but frequency and phase modulation can operate simulta-
neously as the RU/RD function.
POWER SUPPLIES
The AVDD and DVDD supply pins provide power to the DDS
core and supporting analog circuitry. These pins connect to a
1.8 V nominal power supply.
The DVDD_I/O pin connects to a 3.3 V nominal power supply.
All digital inputs are 3.3 V logic except for the CLK_MODE_SEL
input. CLK_MODE_SEL (Pin 24) is an analog input and should
be operated by 1.8 V logic.
SINGLE-TONE MODE
Single-tone mode is the default mode of operation after a master
reset signal. In this mode, all four DDS channels share a common
address location for the frequency tuning word (Register 0x04)
and phase offset word (Register 0x05). Channel enable bits are
provided in combination with these shared addresses. As a
result, the frequency tuning word and/or phase offset word can
be independently programmed between channels (see the
following Step 1 through Step 5). The channel enable bits do not
require an I/O update to enable or disable a channel.
See the Register Maps and Bit Descriptions section for a
description of the channel enable bits in the channel select
register (CSR, Register 0x00). The channel enable bits are
enabled or disabled immediately after the CSR data byte is
written.
Address sharing enables channels to be written simultaneously,
if desired. The default state enables all channel enable bits.
Therefore, the frequency tuning word and/or phase offset word
is common to all channels but written only once through the
serial I/O port.
The following steps present a basic protocol to program a
different frequency tuning word and/or phase offset word for
each channel using the channel enable bits.
1.
Power up the DUT and issue a master reset. A master reset
places the part in single-tone mode and single-bit mode for
serial programming operations (refer to the Serial I/O Modes
of Operation section). Frequency tuning words and phase
offset words default to 0 at this point.
2.
Enable only one channel enable bit (Register 0x00) and
disable the other channel enable bits.
3.
Using the serial I/O port, program the desired frequency
tuning word (Register 0x04) and/or the phase offset word
(Register 0x05) for the enabled channel.
4.
Repeat Step 2 and Step 3 for each channel.
5.
Send an I/O update signal. After an I/O update, all
channels should output their programmed frequency
and/or phase offset value.
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