參數(shù)資料
型號： AD9983AKSTZ-140
廠商： Analog Devices Inc
文件頁數(shù)： 18/44頁
文件大?。?/td> 0K
描述： IC DISPLAY 8BIT 140MSPS 80LQFP
標(biāo)準(zhǔn)包裝： 90
應(yīng)用： 視頻
接口： 模擬
電源電壓： 1.7 V ~ 3.47 V
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 管件
安裝類型： 表面貼裝
AD9983A
Rev. 0 | Page 25 of 44
Hex
Address
Read/Write,
Read Only
Bits
Default
Value
Register Name
Description
4
***0 ****
Clamp Source Select.
0 = Use the internal clamp generated from Hsync
1 = Use the external clamp signal
3
**** 0***
Red Clamp Select.
0 = Clamp the red channel to ground
1 = Clamp the red channel to midscale
2
**** *0**
Green Clamp Select.
0 = Clamp the green channel to ground
1 = Clamp the green channel to midscale
1
**** **0*
Blue Clamp Select.
0 = Clamp the blue channel to ground
1 = Clamp the blue channel to midscale
0
**** ***0
Must be set to 0 for proper operation.
0x19
R/W
7:0
0000 1000
Clamp Placement
Places the clamp signal an integer number of clock periods after
the trailing edge of the Hsync signal.
0x1A
R/W
7:0
0010 0000
Clamp Duration
Number of clock periods that the clamp signal is actively clamping.
0x1B
R/W
7
0*** ****
Clamp and Offset
External Clamp Polarity Override.
0 = The chip selects the clamp polarity
1 = The polarity of the clamp signal is set by Reg. 0x1B, Bit 6
6
*1** ****
External Clamp Input Polarity. This bit is used only if Reg. 0x1B, Bit 7
is set to 1.
0 = Active low external clamp
1 = Active high external clamp
5
**0* ****
Auto-Offset Enable.
0 = Auto-offset is disabled
1 = Auto-offset is enabled (offsets become the desired clamp code)
4:3
***1 1***
Auto-Offset Update Frequency. This selects how often the auto-
offset circuit operates.
00 = every 3 clamps
01 = 48 clamps
10 = every 192 clamps
11 = every 3 Vsyncs
2:0
**** *011
Must be written to default (011) for proper operation.
0x1C
R/W
7:0
1111 1111
TestReg0
Must be set to 0xFF for proper operation.
0x1D
R/W
7:3
0111 1***
SOG Control
SOG Slicer Threshold. Sets the voltage level of the SOG slicer’s
comparator.
2
**** *0**
SOGOUT Polarity. Sets the polarity of the signal on the SOGOUT pin.
0 = Active low SOGOUT
1 = Active high SOGOUT
1:0
**** **00
SOGOUT Select.
00 = Raw SOG from sync slicer (SOGIN0 or SOGIN1)
01 = Raw Hsync (HSYNC0 or HSYNC1)
10 = Regenerated sync from sync filter
11 = Filtered sync from sync filter
0x1E
R/W
7
*** ****
Power
Channel Select Override.
0 = The chip determines which input channels to use
1 = The input channel selection is determined by Reg. 0x1E, Bit 6
6
*0** ****
Channel Select. Input channel select: this is used only if Reg. 0x1E,
Bit 7 is set to 1, or if syncs are present on both channels.
0 = Channel 0 syncs and data are selected
1 = Channel 1 syncs and data are selected
5
**1* ****
Programmable Bandwidth.
0 = Low analog input bandwidth (7 MHz)
1 = High analog input bandwidth
4
***1 ****
Power-Down Control Select.
0 = Manual power-down control
1 = Auto power-down control
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