參數(shù)資料
型號： AD9983AKSTZ-140
廠商： Analog Devices Inc
文件頁數(shù)： 44/44頁
文件大小： 0K
描述： IC DISPLAY 8BIT 140MSPS 80LQFP
標準包裝： 90
應用： 視頻
接口： 模擬
電源電壓： 1.7 V ~ 3.47 V
封裝/外殼： 80-LQFP
供應商設備封裝： 80-LQFP（14x14）
包裝： 管件
安裝類型： 表面貼裝
AD9983A
Rev. 0 | Page 9 of 44
Mnemonic
Function
Description
REFLO, REFHI
Input Amplifier Reference
REFLO and REFHI are connected together through a 10 μF capacitor. These are used for
stability in the input ADC circuitry. See Figure 6.
FILT
External Filter Connection
For proper operation, the pixel clock generator PLL requires an external filter. Connect the
filter shown in Figure 6 to this pin. For optimal performance, minimize noise and parasitics
on this node. For more information, see the PCB Layout Recommendations section.
HSOUT
Horizontal Sync Output
A reconstructed and phase-aligned version of the Hsync input. Both the polarity and
duration of this output can be programmed via serial bus registers. By maintaining
alignment with DATACK and Data, data timing with respect to Hsync can always be
determined.
VSOUT/A0
Vertical Sync Output
Pin shared with A0, serial port address. This can be either a separated Vsync from a
composite signal or a direct pass through of the Vsync signal. The polarity of this output can
be controlled via a serial bus bit. The placement and duration in all modes can be set by the
graphics transmitter or the duration can be set by Register 0x14 and Register 0x15. This pin
is shared with the A0 function, which does not affect Vsync Output functionality. For more
details on A0, see the description in the Serial Control Port section.
Serial Port Address Input 0
Pin shared with VSOUT. This pin selects the LSB of the serial port device address,
allowing two Analog Devices parts to be on the same serial bus. A high impedance
external pull-up resistor enables this pin to be read at power-up as 1, or a high
impedance, external pull-down resistor enables this pin to be read at power-up as a 0
and not interfere with the VSOUT functionality.
SOGOUT
Sync-On-Green Slicer
Output
This pin outputs one of four possible signals (controlled by Register 0x1D, Bits[1:0]): raw
SOG, raw Hsync, regenerated Hsync from the filter, or the filtered Hsync. See Figure 8 to
view how this pin is connected. Other than slicing off SOG, the output from this pin
gets no additional processing on the AD9983A. Vsync separation is performed via the
sync separator.
O/E FIELD
Odd/Even Field Bit for
Interlaced Video
This output will identify whether the current field (in an interlaced signal) is odd or even.
SDA
Serial Port Data I/O
Data I/O for the I2C serial port.
SCL
Serial Port Data Clock
Clock for the I2C serial port.
RED [7:0]
Data Output, Red Channel
GREEN [7:0]
Data Output, Green Channel
BLUE [7:0]
Data Output, Blue Channel
The main data outputs. Bit 9 is the MSB. The delay from pixel sampling time to output is
fixed. When the sampling time is changed by adjusting the phase register, the output
timing is shifted as well. The DATACK and HSOUT outputs are also moved, so the timing
relationship among the signals is maintained.
DATACK
Data Clock Output
This is the main clock output signal used to strobe the output data and HSOUT into
external logic. Four possible output clocks can be selected with Register 0x20, Bits[7:6].
Three of these are related to the pixel clock (pixel clock, 90° phase-shifted pixel clock
and 2× frequency pixel clock). They are produced either by the internal PLL clock
generator or EXTCK and are synchronous with the pixel sampling clock. The fourth
option for the data clock output is an internally generated 12x pixel clock.
The sampling time of the internal pixel clock can be changed by adjusting the phase
register (Register 0x04). When this is changed, the pixel related DATACK timing is also
shifted. The data, DATACK, and HSOUT outputs are all moved so that the timing
relationship among the signals is maintained.
VD (1.8 V)
Main Power Supply
These pins supply power to the main elements of the circuit. They should be as quiet
and filtered as possible.
VDD (1.8 V to 3.3 V)
Digital Output Power Supply
A large number of output pins (up to 29) switching at high speed (up to 140 MHz)
generates a lot of power supply transients (noise). These supply pins are identified
separately from the VD pins, so special care can be taken to minimize output noise
transferred into the sensitive analog circuitry. If the AD9983A is interfacing with lower
voltage logic, VDD can be connected to a lower supply voltage (as low as 1.8 V) for
compatibility.
PVD (1.8 V)
Clock Generator Power
Supply
The most sensitive portion of the AD9983A is the clock generation circuitry. These pins
provide power to the clock PLL and help the user design for optimal performance. The
designer should provide quiet, noise-free power to these pins.
DAVDD (1.8 V)
Digital Input Power Supply
This supplies power to the digital logic.
GND
Ground
The ground return for all circuitry on-chip. It is recommended that the AD9983A be
assembled on a single solid ground plane, with careful attention to ground current paths.
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