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| 型號： | ADA4859-3ACPZ-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP 3CH CFB G=2 W/CP 16LFCSP |
| 標準包裝： | 1 |
| 應(yīng)用： | 電流反饋 |
| 電路數(shù)： | 3 |
| -3db帶寬： | 265MHz |
| 轉(zhuǎn)換速率： | 740 V/µs |
| 電流 - 電源： | 17mA |
| 電流 - 輸出 / 通道： | 19mA |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 16-LFCSP-VQ EP（4x4） |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 768 (CN2011-ZH PDF) |
| 其它名稱： | ADA4859-3ACPZ-R7DKR |
ADA4859-3
Data Sheet
Rev. A | Page 14 of 16
VIDEO LINE DRIVER
The ADA4859-3 was designed to excel in video driver applications.
Figure 36 shows a typical schematic for a video driver operating
on bipolar supplies.
07715-
134
1
2
3
4
11
12
CHARGE
PUMP
10
9
5
6
7
8
16
15
14
13
1F
+
10F
0.1F
+VS
1F
VIN (B)
75
VOUT (B)
75
VOUT (G)
75
VOUT (R)
75
VIN (G)
75
VIN (R)
PD
Figure 36. Video Driver Schematic
In applications that require multiple video loads be driven
simultaneously, the ADA4859-3 can deliver. Figure 37 shows
the ADA4859-3 configured with two video loads, and Figure 38
shows the large signal performance for multiple video loads.
07715-
135
75
CABLE
75
CABLE
75
VOUT2
VOUT1
+VS
0.1F
10F
VIN
75
CABLE
75
+
–
Figure 37. Video Driver Schematic for Two Video Loads
6.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
1
10
100
1000
C
LOS
E
D
-LOOP
GA
IN
(
dB
)
FREQUENCY (MHz)
RL = 150
RL = 75
07715-
034
Figure 38. Large Signal Frequency Response for Various Loads
POWER-DOWN
The ADA4859-3 is equipped with a PD (power-down) pin for
all three amplifiers. This allows the user the ability to reduce the
quiescent supply current when an amplifier is not active. The
power-down threshold levels are derived from ground level.
The amplifiers are powered down when the voltage applied to
the PD pin is greater than a certain voltage from ground. In a 5 V
supply application, the voltage is greater than 2 V, and in a 3.3 V
supply application, the voltage is greater than 1.5 V. The amplifier
is enabled whenever the PD pin is connected to ground. If the
PD pin is not used, it is best to connect it to ground. Note that
the power-down feature does not control the charge pump output
voltage and current.
Table 5. Power-Down Voltage Control
PD Pin
5 V
3.3 V
Not Active
<1.5 V
<1 V
Active
>2 V
>1.5 V
LAYOUT CONSIDERATIONS
As is the case with all high speed applications, careful attention
to printed circuit board (PCB) layout details prevents associated
board parasitics from becoming problematic. Proper RF design
technique is mandatory. The PCB should have a ground plane
covering all unused portions of the component side of the board to
provide a low impedance return path. Removing the ground
plane on all layers from the area near the input and output pins
reduces stray capacitance. Locate termination resistors and loads as
close as possible to their respective inputs and outputs. Keep
input and output traces as far apart as possible to minimize
coupling (crosstalk) through the board. Adherence to microstrip or
stripline design techniques for long signal traces (greater than
about 1 inch) is recommended.
POWER SUPPLY BYPASSING
Careful attention must be paid to bypassing the power supply pins
of the ADA4859-3. Use high quality capacitors with low equivalent
series resistance (ESR), such as multilayer ceramic capacitors
(MLCCs), to minimize supply voltage ripple and power dissipation.
A large, usually tantalum, 10 F to 47 F capacitor located in
proximity to the ADA4859-3 is required to provide good
decoupling for lower frequency signals. In addition, locate 0.1 F
MLCC decoupling capacitors as close to each of the power supply
pins as is physically possible, no more than 1/8-inch away. The
ground returns should terminate immediately into the ground
plane. Locating the bypass capacitor return close to the load
return minimizes ground loops and improves performance.
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