參數(shù)資料
型號(hào): ADA4899-1YCPZ-RL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 18/21頁(yè)
文件大?。?/td> 0K
描述: IC OPAMP VF ULN ULDIST 8LFCSP
產(chǎn)品培訓(xùn)模塊: Practical Guide High Speed PCB Layout
設(shè)計(jì)資源: High Speed, Precision, Differential AC-Coupled Drive Circuit for AD7625 (CN0080)
標(biāo)準(zhǔn)包裝: 5,000
放大器類型: 電壓反饋
電路數(shù): 1
轉(zhuǎn)換速率: 310 V/µs
-3db帶寬: 600MHz
電流 - 輸入偏壓: 6µA
電壓 - 輸入偏移: 35µV
電流 - 電源: 14.7mA
電流 - 輸出 / 通道: 200mA
電壓 - 電源,單路/雙路(±): 4.5 V ~ 12 V,±2.25 V ~ 6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-VFDFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 8-LFCSP-VD(3x3)
包裝: 帶卷 (TR)
ADA4899-1
Rev. B | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
Supply Voltage
12.6 V
Power Dissipation
Differential Input Voltage
±1.2 V
Differential Input Current
±10 mA
Storage Temperature Range
–65°C to +150°C
Operating Temperature Range
–40°C to +125°C
Lead Temperature (Soldering 10 sec)
300°C
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4899-1
package is limited by the associated rise in junction temperature
(TJ) on the die. The plastic encapsulating the die locally reaches
the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit may change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the ADA4899-1.
Exceeding a junction temperature of 150°C for an extended
period can result in changes in silicon devices, potentially
causing failure.
The still-air thermal properties of the package and PCB (θJA),
the ambient temperature (TA), and the total power dissipated in
the package (PD) determine the junction temperature of the die.
The junction temperature is calculated as
TJ = TA + (PD × θJA)
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming the load (RL) is referenced to
midsupply, the total drive power is VS/2 × IOUT, some of which is
dissipated in the package and some in the load (VOUT × IOUT).
The difference between the total drive power and the load
power is the drive power dissipated in the package.
PD = Quiescent Power + (Total Drive Power – Load Power)
()
L
OUT
L
OUT
S
D
R
V
R
V
I
V
P
2
2
×
+
×
=
RMS output voltages should be considered. If RL is referenced to
VS–, as in single-supply operation, the total drive power is VS ×
IOUT. If the rms signal levels are indeterminate, consider the
worst case, when VOUT = VS/4 for RL to midsupply
() (
)
L
S
D
R
/
V
I
V
P
2
4
+
×
=
In single-supply operation with RL referenced to VS–, worst case
is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θJA. Soldering the exposed paddle to the ground
plane significantly reduces the overall thermal resistance of the
package.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the exposed paddle
(EPAD) 8-lead SOIC (70°C/W) and 8-lead LFCSP (70°C/W)
packages on a JEDEC standard 4-layer board. θJA values are
approximations.
05
720-
00
3
AMBIENT TEMPERATURE (°C)
120
–40
–20
0
204060
80
100
MA
XI
M
U
M
PO
W
E
R
D
ISS
IP
A
T
IO
N
(
W
)
0.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
LFCSP AND SOIC
Figure 4. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
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