參數(shù)資料
型號(hào)： ADA4922-1ARDZ-R7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 16/20頁(yè)
文件大?。?/td> 0K
描述： IC ADC DRIVER 18BIT DIFF 8-SOIC
標(biāo)準(zhǔn)包裝： 1,000
類(lèi)型： ADC 驅(qū)動(dòng)器
應(yīng)用： 數(shù)據(jù)采集
安裝類(lèi)型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm Width）裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 8-SOIC-EP
包裝： 帶卷 (TR)
ADA4922-1
Rev. 0 | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
Supply Voltage
26 V
Power Dissipation
Storage Temperature Range
–65°C to +125°C
Operating Temperature Range
–40°C to +85°C
Lead Temperature Range (Soldering 10 sec)
300°C
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for a device soldered in the circuit board with its
exposed paddle soldered to a pad on the PCB surface that is
thermally connected to a copper plane, with zero airflow.
Table 4. Thermal Resistance
Package Type
θJA
θJC
Unit
8-Lead SOIC with EP on 4-layer board
79
25
°C/W
8-Lead LFCSP with EP on 4-layer board
81
17
°C/W
Maximum Power Dissipation
The maximum safe power dissipation in the ADA4922-1
package is limited by the associated rise in junction temperature
(TJ) on the die. At approximately 150°C, which is the glass
transition temperature, the plastic changes its properties. Even
temporarily exceeding this temperature limit can change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the ADA4922-1. Exceeding a
junction temperature of 150°C for an extended period can
result in changes in the silicon devices potentially causing
failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The power dissipated due to the load
drive depends upon the particular application. For each output,
the power due to load drive is calculated by multiplying the load
current by the associated voltage drop across the device. The
power dissipated due to all of the loads is equal to the sum of
the power dissipation due to each individual load. RMS voltages
and currents must be used in these calculations.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θJA. The exposed paddle on the underside of the
package must be soldered to a pad on the PCB surface that is
thermally connected to a copper plane to achieve the specified θJA.
Figure 3 shows the maximum safe power dissipation in the
packages vs. the ambient temperature for the 8-lead SOIC
(79°C/W) and for the 8-lead LFCSP (81°C/W) on a JEDEC
standard 4-layer board, each with its underside paddle soldered
to a pad that is thermally connected to a PCB plane. θJA values
are approximations.
3.0
0
–40
80
05681-041
AMBIENT TEMPERATURE (
°C)
M
A
XIM
U
M
POW
E
R
D
ISSIPA
TION
(
W
)
2.5
2.0
1.5
1.0
0.5
–20
0
20
40
60
SOIC
LFCSP
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
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