參數(shù)資料
型號(hào): ADADC80-Z-12
廠商: Analog Devices Inc
文件頁(yè)數(shù): 5/16頁(yè)
文件大小: 0K
描述: IC ADC 12BIT INTEGRATED 32-CDIP
標(biāo)準(zhǔn)包裝: 1
位數(shù): 12
采樣率(每秒): 40k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 800mW
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -25°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 32-CDIP(0.910",23.12mm)
供應(yīng)商設(shè)備封裝: 32-CDIP 側(cè)面銅焊
包裝: 管件
輸入數(shù)目和類型: 2 個(gè)單端,單極;2 個(gè)單端,雙極
ADADC80
Rev. E | Page 13 of 16
CONTROL MODES
The timing sequence of the ADADC80 allows the device to be
easily operated in a variety of systems with different control
modes. The most common control modes are illustrated in
BIT 11
SHORT
CYCLE
CLOCK
INHIBIT
EXTERNAL
CLOCK IN
CONVERT
START
EXTERNAL
CLOCK
ADADC80
28
21
19
10-BIT
OPERATION
12-BIT
OPERATION
5V
01
20
2-
01
6
BIT 11
SHORT
CYCLE
CONVERT
START
CONVERT
COMMAND
ADADC80
CLOCK
INHIBIT
EXTERNAL
CLOCK IN
28
21
20
19
18
10-BIT
OPERATION
12-BIT
OPERATION
5V
Figure 16. Internal Clock—Normal Operating Mode,
Conversion Initiated by the Rising Edge of Convert Command
(Internal Clock Runs Only During Conversion)
0
120
2-
01
7
20
DIGITAL
COMMON
DIGITAL
18
COMMON
Figure 17. Continuation Conversion with External Clock Conversion Initiated
by 14th Clock Pulse (Clock Runs Continuously)
01
20
2-
01
8
BIT 11
SHORT
EXTERNAL
CLOCK IN
STATUS
EXTERNAL
CLOCK
CONV
COMM
ADADC80
CYCLE
CLOCK
INHIBIT
CONVERT
START
ERT
AND
28
20
19
22
18
10-BIT
OPERATION
12-BIT
OPERATION
5V
DIGITAL
COMMON
21
Figure 18. Continuous External Clock Conversion Initiated by Rising Edge of
Convert Command (Convert Command Must Be Synchronized with Clock)
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