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參數(shù)資料
| 型號： | ADAV801ASTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Audio Codec for Recordable DVD |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO64 |
| 封裝： | ROHS COMPLIANT, MS-026BCD, LQFP-64 |
| 文件頁數(shù)： | 39/56頁 |
| 文件大?。?/td> | 1405K |
| 代理商： | ADAV801ASTZ |
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ADAV801
Table 40. Receiver Error Mask Register
Rev. 0 | Page 39 of 56
RxValid
Mask
7
Emphasis
Mask
6
nAudio
Mask
5
onA
Preamble
Mask
4
CRCError
Mask
3
Stream
Mask
2
BiPhas
Parity
Mask
1
Lock Mask
0
ADDRESS = 0011001 (0x19)
RxValidity Mask
Emphasis Mask
NonAudio Mas
NonAudio Preamble
Mask
CRCError M
ity
No
N
udio
No
e/
rating an interrupt.
Masks the RxValidity bit from gene
0 = RxValidity bit does not generate an interrupt.
1 = RxValidity bit generates an interrupt.
Masks the emphasis bit from generating an in
0 = Emphasis bit does not generate an interrupt.
1 = Emphasis bit generates an interrupt.
Masks the NonAudio bit from generating
terrupt.
k
an interrupt.
0 = NonAudio bit does not generate an interrupt.
1 = NonAudio bit generates an interrupt.
nAudio preamble bit from generating an interrupt.
Masks the No
0 = NonAudio preamble bit does not gene
onAudio preamble bit generates an interrupt.
1 = N
Masks the CRCError bit from generating an interrupt.
0 = CRCError bit does not generate an interrupt.
1 = CRCError bit generates an interrupt.
Masks the NoStream bit from generating an interrupt.
0 = NoStream bit does not generate an interrupt.
1 = NoStream bit generates an interrupt.
Masks the BiPhase/Parity bit from generating
0 = BiPhase/Parity bit does not generate an interrupt.
1 = BiPhase/Parity bit generates an interrupt.
Masks the Lock bit from generating an interrupt.
0 = Lock bit does not generate an interrupt.
1 = Lock bit generates an interrupt.
e an interru
rat
ask
NoStream Mask
BiPhase/Parity Mask
an interrupt.
Lock Mask
pt.
Table 41. Sample Rate Co
ADDRESS = 0011010 (0x1A)
TOO_SLOW
RES
7
RES
6
RES
5
RES
4
TOO_SLOW
3
OVRL
2
OVRR
1
MUTE_IND
0
nverter Error Register (Read Only)
This bit is set, when the clock to the SRC is too slow, that is, there are not enough clock cycles to complete the
internal convolution.
This bit is set, when the left output data of the sample rate converter has gone over the full-scale range and has been
clipped. This bit is not cleared until the register is read.
This bit is set, when the right output data of the sample rate converter has gone over the full-scale range and has
been clipped. This bit is not cleared until the register is read.
Mute indicated. This bit is set, when the SRC is in fast mode and clicks or pops can be heard in the SRC output data.
The output of the SRC can be muted, if required, until the SRC is in slow mode. Once read, this bit remains in its state
and does not generate an interrupt until it has changed state.
OVRL
OVRR
MUTE_IND
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADAV801ASTZ-REEL | 功能描述:IC CODEC AUDIO R-DVD 3.3V 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| ADAV802AST | 制造商:Analog Devices 功能描述:AUDIO CODEC FOR RECORDABLE DVD - Bulk |
| ADAV802ASTZ | 制造商:Analog Devices 功能描述: |
| ADAV803 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Audio Codec for Recordable DVD |
| ADAV803AST | 制造商:Analog Devices 功能描述:AUDIO CODEC FOR RECORDABLE DVD - Bulk |
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