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參數(shù)資料
| 型號： | ADC-318A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:85; Series:LJT00R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:23; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:23-2 |
| 中文描述： | 8位，120MHz的和140MHz的全閃光的A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 285K |
| 代理商： | ADC-318A |
ADC-318, ADC-318A
4
Figure 2-3: A/D Clock Input Connection
Figure 2-4: Digital Input/Output Connections
SIGNAL
INPUT
VOLTAGE
DIGITAL OUTPUT CODE (A,B OUTPUT)
INV=1
LSB
MSB
INV=0
LSB
MSB
VRT
VRM2
11111111
10000000
01111111
00000000
00000000
01111111
10000000
11111111
VRB
Table 4: Digital Output Coding
DIGITAL INPUT
LEVEL
SUPPLY
VOLTAGES
–DVS
DGND3
TTL
PECL
ECL
0V
0V
–5V
+5V
+5V
0V
+5V
+5V
±5V
Table 3: Logic Input Level vs. Power Supply Settings
11
12
13
14
15
16
17
18
TTL LEVEL CLOCK INPUT
A/D CLOCK
A/D CLOCK
A/D CLOCK
ECL, PECL LEVEL CLOCK INPUTS
ADC-318
TTL LEVEL RESET INPUT
RSET
RSET
RSET
ECL, PECL LEVEL
RESET INPUTS
2
1
48
47
46
45
44
43
42
TTL CLOCK OUT
COMPLEMENTARY BINARY
STRAIGHT BINARY
OUTPUT CODING
STRAIGHT DATA OUT
DEMULTIPLEXED DATA OUT
A/D CONVERSION MODE
5V(D)
5V(D)
ADC-318
ADC-318A
the reference input voltages given to VRT and VRB. Keep
the ranges of V within values shown in this data sheet.
Standard settings are VRT = +4.0V, V input range from
+2 to +4V. This setting can be varied to VRT = +3.5V,
VRB = +2V and 1.5V p-p analog input range, depending
on your selection of amplifiers which may provide less
than +4V output.
5. The ADC-318 and ADC-318A have resistor matrix taps at
VRM1 (pin 4), VRM2 (pin 7) and VRM3 (pin 9). These pins
provide , and full scale of VRT-VRB voltage respec-
tively. These outputs may be used to adjust the integral
non-linearity. Bypass these pins to GND with 0.1uF ceramic
chip capacitors.
6. A/D CLK input and RSET/RSET inputs are TTL or ECL,
PECL (Positive ECL) compatible. Pins are provided
individually. TTL or PECL is available with +5V single power
applied. ECL is available with ±5V dual power applied. The
connections of –DVs (pin 1) and DGND3 (pin12) are
different depending on the power supply mode used. Refer
to Figures 2-1 and 2-2.
a. For +5V single power (TTL or PECL) –DVs (pin 1) is
connected to DGND. DGND3 (pin 12) is connected
to +5V power.
b. For ±5V dual power (ECL) –DVs (pin 1) is connected
to –5V power. DGND3 (pin 12) is connected to DGND.
7. When the A/D CLK is driven with ECL or PECL, A/D CLK
(pin 13) and A/D CLK (pin 14) are to be driven by differen-
tial logic inputs to avoid unstable performance at critically
high speeds. If a risk of unstable performance is accept-
able, single logic input can be used opening A/D CLK (pin
14). The A/D CLK pin should be bypassed to DGND with a
0.1uF ceramic capacitor. When connected this way there
will be a voltage of DGND –1.2V on the A/D CLK pin. This
voltage can not be used as a threshold voltage for ECL or
PECL. Input the A/D CLK pulse to pin 15 when TTL is
selected.
8. The ADC-318 and ADC-318A have RSET/RSET input pins.
An internal frequency half divider can be initialized with
inputs to these pins. With ECL or PECL, differential inputs
are given to RSET (pin 48) and RSET (pin 47). This
function can be achieved with a single input, leaving pin 47
open and bypassing to DGND with a 0.1uF ceramic chip
capacitor. The voltage level of pin 47 is the threshold
voltage of ECL or PECL. Use RSET (pin 46) for TTL.
9. SELECT (pin 45) is used to set output mode. Connection of
this pin to DGND selects the straight output mode and
connection to +DVs selects the 1:2 de-multiplexed output
mode. The maximum sampling rates are 100MHz for straight
mode (For both models, ADC-318 and ADC-318A) and
120MHz (ADC-318) and 140MHz (ADC-318A) for de-
multiplexed mode. Refer to figure 2-4. There is an applica-
tion where a multiple number of ADC-318/318A's are used
with a common A/D CLK and outputs are in de-multiplexed
mode. In this case, the initial conditions of the frequency half
divider of each A/D Converter are not synchronized and it is
possible that each converter may have one clock maximum
of timing lag. This lag can be avoided by giving a common
RSET pulse to all converters at power ON. (See Figure 3-3
and 3-4, timing diagrams.)
10.The ADC-318 and ADC-318A have a TTL compatible CLK
OUT (pin 43). Since the rising edge of this pulse can provide
Setup and Hold time of output data, regardless of the output
mode, this signal can be used as synchronization pulse for
external circuits. Data output timing is different for the
straight mode and the de-multiplexed mode. See the timing
chart Figure 3.
11. INV (pin 44) is used to invert polarity of the TTL compatible
output data from both A and B ports. Leaving this pin open
or connected to +DVs makes the output positive true and
connection to DGND makes it negative true logic. See
input/output code table, Table 4.
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