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參數(shù)資料
| 型號： | ADC-321 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:24; Series:LJT00R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle |
| 中文描述： | 8位，50MHz的視頻A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 174K |
| 代理商： | ADC-321 |
ADC-321
4
Figure 2-1. ADC-321 Timing Diagram
Figure 2-2. ADC-321 Timing Diagram
V
IN
MSB
LSB
Table 2: Digital Output Coding
OUTPUT CODE
0V
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
+7.812mV
+0.9922V
+1.000V
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
+1.500V
1
1
0
0
0
0
0
0
+1.9922V
1
1
1
1
1
1
1
1
THEORY OF OPERATION
(See Functional Block Diagram, Figure 1, and Timing
Diagrams, Figure 2)
1. The DATEL ADC-321 is a 2-step parallel A/D converter
featuring a 4-bit upper comparator group and two 4-bit
lower comparator groups, each with built-in sample and
hold. A reference voltage equal to the voltage between
(V
RT
– V
RB
)/16 is constantly applied to the 4-bit upper
comparator block. A voltage corresponding to the upper
data is fed through the reference supply to the lower data.
V
RTS
and V
RBS
pins provde the self generation function for
V
RT
(reference voltage top) and V
RB
(reference voltage
bottom) voltages.
2. This converter uses an offset cancelation type comparator
and operates synchronously with the external clock. It
features various operating modes which are shown in the
Timing Diagram (Figure 2) by the symbols S, H and C.
These characters stand for Input
S
ampling (Auto Zero)
Mode, Input
H
old Mode and
C
omparison Mode.
3. The operation of the respective parts is as indicated in
Figure 2-3. For instance, input voltage N is sampled with
the falling edge of the first clock by means of the upper
comparator block and the lower comparator A block. Input
voltage N+1 is sampled with the falling edge of the second
clock by means of the upper comparator block and lower
comparator B block. The upper comparator block finalizes
comparison data UD(N) with the rising edge of the second
clock. The lower comparator block finalizes comparison
data LD(N) with the rising edge of the third clock. UD(N)
and LD(N) are combined and routed to the output as Output
Data N with the rising edge of the fourth clock. Thus there
is a 2.5 clock delay from the analog input sampling point to
the digital data output.
1.3V
tr = 4.5ns
90%
10%
V
OL
t
phz
t
plz
90%
tr = 4.5ns
10%
t
pzh
1.3V
1.3V
t
pzl
0V
3V
V
OH
/(=DGND)
/(=DGND)
V
OL
V
OH
OE INPUT
OUTPUT 1
OUTPUT 2
CLOCK 1.3V
tr = 4ns
tf = 4ns
90%
10%
DATA
OUTPUTS
0. 3 DV
S
0. 7 DV
S
t
pLH
t
pHL
3V
0V
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