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參數(shù)資料
| 型號(hào)： | ADC0800 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | ECONOLINE: REC3-S_DRW(Z)/H* - 3W DIP Package- 1kVDC Isolation- Wide Input 2:1 & 4:1- Regulated Output- 100% Burned In- UL94V-0 Package Material- Continuous Short Circiut Protection- Efficiency to 80% |
| 中文描述： | ADC0800 8位A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大小： | 166K |
| 代理商： | ADC0800 |
Application Hints
(Continued)
CMOS will satisfy this requirement but a pull-up resistor
should be used for TTL logic inputs.
RE-START AND DATA VALID AFTER EOC
The EOC line (pin 9) will be in the low state for a maximum
of 40 clock periods to indicate ‘‘busy’’. A START pulse that
occurs while the A/D is BUSY will reset the SAR and start a
new conversion with the EOC signal remaining in the low
state until the end of this new conversion. When the conver-
sion is complete, the EOC line will go to the high voltage
state. An additional 4 clock periods must be allowed to
elapse after EOC goes high, before a new conversion cycle
is requested. Start Conversion pulses that occur during this
last 4 clock period interval may be ignored (seeFigure 1 and
2 for high speed operation). This is a problem only for high
conversion rates and keeping the number of conversions
per second less than f
CLOCK
/44 automatically guarantees
proper operation. For example, for an 800 kHz clock, ap-
proximately 18,000 conversions per second are allowed.
The transfer of the new digital data to the output is initiated
when EOC goes to the high voltage state.
POWER SUPPLIES
Standard
V
DD
e
0V. Device accuracy is dependent on stability of the
reference voltage and has slight sensitivity to V
SS
DV
GG
.
V
DD
has no effect on accuracy. Noise spikes on the V
SS
and V
GG
supplies can cause improper conversion; there-
fore, filtering each supply with a 4.7
m
F tantalum capacitor is
recommended.
supplies
are
V
SS
ea
5V,
V
GG
eb
12V
and
CONTINUOUS CONVERSIONS AND LOGIC CONTROL
Simply tying the EOC output to the Start Conversion input
will allow continuous conversions, but an oscillation on this
line will exist during the first 4 clock periods after EOC goes
high. Adding a D flip-flop between EOC (D input) to Start
Conversion (Q output) will prevent the oscillation and will
allow a stop/continuous control via the ‘‘clear’’ input.
To prevent missing a start pulse that may occur after EOC
goes high and prior to the required 4 clock period time inter-
val, the circuit ofFigure 1 can be used. The RS latch can be
set at any time and the 4-stage shift register delays the
application of the start pulse to the A/D by 4 clock periods.
The RS latch is reset 1 clock period after the A/D EOC
signal goes to the low voltage state. This circuit also pro-
vides a Start Conversion pulse to the A/D which is 1 clock
period wide.
A second control logic application circuit is shown in Figure
2. This allows an asynchronous start pulse of arbitrary
length less than T
C
, to continuously convert for a fixed high
level and provides a single clock period start pulse to the
A/D. The binary counter is loaded with a count of 11 when
the start pulse to the A/D appears. Counting is inhibited
until the EOC signal from the A/D goes high. A carry pulse
is then generated 4 clock periods after EOC goes high and
is used to reset the input RS latch. This carry pulse can be
used to indicate that the conversion is complete, the data
has transferred to the output buffers and the system is
ready for a new conversion cycle.
TL/H/5670–3
FIGURE 1. Delaying an Asynchronous Start Pulse
TL/H/5670–10
FIGURE 2. A/D Control Logic
4
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