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參數(shù)資料
| 型號： | ADC10061CIWM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 10-Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold |
| 中文描述： | 1-CH 10-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO20 |
| 封裝： | SOP-20 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 333K |
| 代理商： | ADC10061CIWM |
Applications Information
(Continued)
4.0 INHERENT SAMPLE-AND-HOLD
Because
the ADC10061, ADC10062,
sample the input signal once during each conversion, they
are capable of measuring relatively fast input signals without
the help of an external sample-hold. In a non-sampling
successive-approximation A/D converter, regardless of
speed, the input signal must be stable to better than
±
1/2
LSB during each conversion cycle or significant errors will
result. Consequently, even for many relatively slow input sig-
nals, the signals must be externally sampled and held con-
stant during each conversion if a SAR with no internal
sample-and-hold is used.
Because they incorporate a direct sample/hold control input,
the ADC10061, ADC10062, and ADC10064 are suitable for
use in DSP-based systems. The S/H input allows synchroni-
zation of the A/D converter to the DSP system’s sampling
rate
and
to
other
ADC10061s,
ADC10064s.
TheADC10061,ADC10062, andADC10064 can perform ac-
curate conversions of input signals with frequency compo-
nents from DC to over 160 kHz.
and ADC10064
ADC10062s,
and
5.0 POWER SUPPLY CONSIDERATIONS
The ADC10061, ADC10062, and ADC10064 are designed to
operate from a +5V (nominal) power supply. There are two
supply pins, AV
and DV
. These pins allow separate ex-
ternal bypass capacitors for the analog and digital portions of
the circuit. To guarantee accurate conversions, the two sup-
ply pins should be connected to the same voltage source,
and each should be bypassed with a 0.1 μF ceramic capaci-
tor in parallel with a 10 μF tantalum capacitor. Depending on
the circuit board layout and other system considerations,
more bypassing may be necessary.
The ADC10061 has a single ground pin, and the ADC10062
and ADC10064 each have separate analog and digital
ground pins for separate bypassing of the analog and digital
supplies. The devices with separate analog and digital
ground pins should have their ground pins connected to the
same potential, and all grounds should be “clean” and free of
noise.
In systems with multiple power supplies, careful attention to
power supply sequencing may be necessary to avoid over-
driving inputs. The A/D converter’s power supply pins should
be at the proper voltage before digital or analog signals are
applied to any of the other pins.
6.0 LAYOUT AND GROUNDING
In order to ensure fast, accurate conversions from the
ADC10061, ADC10062, and ADC10064, it is necessary to
use appropriate circuit board layout techniques. The analog
ground return path should be low-impedance and free of
noise from other parts of the system. Noise from digital cir-
cuitry can be especially troublesome, so digital grounds
should always be separate from analog grounds. For best
performance, separate ground planes should be provided for
the digital and analog parts of the system.
All bypass capacitors should be located as close to the con-
verter as possible and should connect to the converter and
to ground with short traces. The analog input should be iso-
lated from noisy signal traces to avoid having spurious sig-
nals couple to the input. Any external component (e.g., a fil-
ter capacitor) connected across the converter’s input should
be connected to a very clean ground return point. Grounding
the component at the wrong point will result in reduced con-
version accuracy.
7.0 DYNAMIC PERFORMANCE
Many applications require the A/D converter to digitize AC
signals, but conventional DC integral and differential nonlin-
earity specifications don’t accurately predict the A/D convert-
er’s performance with AC input signals. The important speci-
fications for AC applications reflect the converter’s ability to
DS011020-15
FIGURE 4. Typical Connection. Note the multiple bypass capacitors on the reference and power supply pins. If V
REF
is not grounded, it should also be bypassed to analog ground using multiple capacitors (see 5.0 “Power Supply
Considerations”). AGND and DGND should be at the same potential. V
is shown with an input protection network.
Pin 17 is normally left open, but optional “speedup” resistor R
SA
can be used to reduce the conversion time.
www.national.com
11
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| ADC10061CIWM/NOPB | 功能描述:IC ADC 10BIT W/MUX 20-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| ADC10061CIWMX | 功能描述:IC ADC 10BIT W/MUX 20-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| ADC10061CIWMX/NOPB | 制造商:Texas Instruments 功能描述:ADC Single Pipelined 800ksps 10-bit Parallel 20-Pin SOIC W T/R |
| ADC10061CMJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 10-Bit |
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