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參數(shù)資料
| 型號(hào)： | ADC10061CIWM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 10-Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold |
| 中文描述： | 1-CH 10-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO20 |
| 封裝： | SOP-20 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大小： | 333K |
| 代理商： | ADC10061CIWM |
Pin Descriptions
DV
CC
, AV
CC
These are the digital and analog positive sup-
ply voltage inputs. They should always be con-
nected to the same voltage source, but are
brought out separately to allow for separate
bypass capacitors. Each supply pin should be
bypassed with a 0.1 μF ceramic capacitor in
parallel with a 10 μF tantalum capacitor to
ground.
INT
This is the active low interrupt output. INT
goes low at the end of each conversion, and
returns to a high state following the rising edge
of RD.
S/H
This is the Sample/Hold control input. When
this pin is forced low (and CS is low), it causes
the analog input signal to be sampled and ini-
tiates a new conversion.
RD
This is the active low Read control input.
When this RD and CS are low, any data
present in the output registers will be placed
on the data bus.
CS
This is the active low Chip Select control input.
When low, this pin enables the RD and S/H
pins.
S0, S1
On the multiple-input devices (ADC10062 and
ADC10064), these pins select the analog input
that will be connected to the A/D during the
conversion. The input is selected based on the
state of S0 and S1 when S/H makes its
High-to-Low transition (See the Timing Dia-
grams). The ADC10064 includes both S0 and
S1. The ADC10062 includes just S0, and the
ADC10061 includes neither.
V
REF
,
V
REF+
may be placed at any voltage between GND
and V
, but V
must be greater than
V
. An input voltage equal to V
pro-
duces an output code of 0, and an input volt-
age equal to (V
1 LSB) produces an out-
put code of 1023.
These are the reference voltage inputs. They
V
IN
, V
IN0
,
V
IN1
, V
IN2
,
V
IN3
These
ADC10061 has one input (V
), theADC10062
has two inputs (V
and V
IN1
), and the
ADC10064 has four inputs (V
, V
, V
and V
). The impedance of the source
should be less than 500
for best accuracy
and conversion speed. For accurate conver-
sions, no input pin (even one that is not se-
lected) should be driven more than 50 mV
above V
CC
or 50 mV below ground.
These are the power supply ground pins. The
ADC10061 has a single ground pin (GND),
and the ADC10062 and ADC10064 have
separate analog and digital ground pins
(AGND and DGND) for separate bypassing of
the analog and digital supplies. The ground
pins
should
be
connected
noise-free system ground. For the devices
with two ground pins, both pins should be re-
turned to the same potential.
These are the TRI-STATE
output pins.
SPEED ADJ (ADC10062 and ADC10064 only). This pin is
normally left unconnected, but by connecting a
resistor between this pin and ground, the con-
version time can be reduced. See the Typical
Performance Curves and the table of Electri-
cal Characteristics.
are
the
analog
input
pins.
The
GND, AGND,
DGND
to
a
stable,
DB0–DB9
www.national.com
3
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