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參數(shù)資料
| 型號： | ADC10838CIN |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | 10-Bit Plus Sign Serial I/O A/D Converters with MUX, Sample/Hold and Reference |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDIP24 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 6/30頁 |
| 文件大?。?/td> | 453K |
| 代理商： | ADC10838CIN |
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Electrical Characteristics
(Continued)
The following specifications apply for V
a
e
AV
a
e
DV
a
e a
5.0 V
DC
, V
REF
a
e a
4.096 V
DC
, V
REF
b
e
V
IN
e
GND,
V
b
e b
5.0 V
DC
, and f
CLK
e
2.5 MHz unless otherwise specified.
Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
;
all other limits T
A
e
T
J
25
§
C. (Note 16)
Symbol
Parameter
Conditions
Typical
(Note 11)
Limits
(Note 12)
Units
(Limits)
AC CHARACTERISTICS
f
CLK
Clock Frequency
3.0
5
2.5
MHz(max)
kHz(min)
Clock Duty Cycle
40
60
%(min)
%(max)
t
C
Conversion Time
12
12
Clock
Cycles
m
s(max)
5
5
t
A
Acquisition Time
4.5
4.5
Clock
Cycles
m
s(max)
2
2
t
SCS
CS Set-Up Time, Set-Up Time from Falling Edge of
CS to Rising Edge of Clock
14
30
ns(min)
(max)
(1 t
CLK
b
14 ns)
(1 t
CLK
b
30 ns)
t
SDI
DI Set-Up Time, Set-Up Time from Data Valid on
DI to Rising Edge of Clock
16
25
ns(min)
t
HDI
DI Hold Time, Hold Time of DI Data from Rising
Edge of Clock to Data not Valid on DI
2
25
ns(min)
t
AT
DO Access Time from Rising Edge of CLK When
CS is ‘‘Low’’ during a Conversion
30
50
ns(min)
t
AC
DO or SARS Access Time from CS, Delay from
Falling Edge of CS to Data Valid on DO or SARS
30
70
ns(max)
t
DSARS
Delay from Rising Edge of Clock to Falling Edge of
SARS when CS is ‘‘Low’’
100
200
ns(max)
t
HDO
DO Hold Time, Hold Time of Data on DO after
Falling Edge of Clock
20
45
ns(max)
t
AD
DO Access Time from Clock, Delay from Falling
Edge of Clock to Valid Data of DO
40
80
ns(max)
t
1H
, t
0H
Delay from Rising Edge of CS to DO or SARS
TRI-STATE
40
50
ns(max)
t
DCS
Delay from Falling Edge of Clock to Falling Edge of
CS
20
30
ns(min)
t
CS(H)
CS ‘‘HIGH’’ Time for A/D Reset after Reading of
Conversion Result
1 CLK
1 CLK
cycle(min)
t
CS(L)
ADC10731 Minimum CS ‘‘Low’’ Time to Start a
Conversion
1 CLK
1 CLK
cycle(min)
t
SC
Time from End of Conversion to CS Going ‘‘Low’’
5 CLK
5 CLK
cycle(min)
t
PD
Delay from Power-Down command to 10% of
Operating Current
1
m
s
t
PC
Delay from Power-Up Command to Ready to Start
a New Conversion
10
m
s
C
IN
Capacitance of Logic Inputs
7
pF
C
OUT
Capacitance of Logic Outputs
12
pF
6
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| ADC108S022CIMT/NOPB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8CH,50KSPS-200KSPS, 10B ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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