參數(shù)資料
型號: ADC12081CIVT
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: ADC
英文描述: 12-Bit, 5 MHz Self-Calibrating, Pipelined A/D Converter
中文描述: 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32
封裝: LQFP-32
文件頁數(shù): 12/16頁
文件大?。?/td> 352K
代理商: ADC12081CIVT
Applications Information
(Continued)
2.3 OE Pin
The OE pin is used to control the state of the out-
puts. When the OE pin is low, the output buffers go into the
active state. When the OE input is high, the output buffers
are in the high impedance state.
2.4 PD Pin
The PD pin, when high, holds the ADC12081 in
a power-down mode where power consumption is typically
less than 15 mW to conserve power when the converter is
not being used. The ADC12081 will begin normal operation
within t
after this pin is brought low, provided a valid
CLOCK input is present. The data in the pipeline is corrupted
while in the power down mode. TheADC12081 should be re-
calibrated after a power-down cycle to ensure optimum per-
formance.
3.0 Outputs
The ADC12081 has three analog outputs: reference output
voltages V
, V
, and V
. There are 14 digital outputs:
12 Data Output pins, Ready and OR (Out of range).
3.1 Reference Output Voltages
The reference output volt-
ages are made available only for the purpose of bypassing
with capacitors to a clean analog ground. The recommended
bypass capacitors are 0.1μF ceramic chip capacitors. Do not
load these pins.
3.2 Ready Output
The Ready output goes high to indicate
that the converter is ready for operation. This signal will go
low when the converter is Calibration or Power Down made.
3.3 OR (Out of Range) Output
The OR output goes high
when the analog input is below GND or above V
. This
output is low when the input signal is in the valid range of op-
eration (0V
V
IN
V
REF
).
3.4 Data Outputs
The Data Outputs are TTL/CMOS com-
patible. The output data format is 12 bits straight binary.
Minimizing the digital output currents will help to minimize
noise due to output switching. This can be done by connect-
ing buffers between the ADC outputs and any other circuitry.
Only one buffer input should be connected to each output.
Additionally, inserting series resistors of 47 to 56 Ohms right
at the digital outputs, close to the ADC pins, will isolate the
outputs from other circuitry and limit output currents.
4.0 Power Supply Considerations
Each power pin should be bypassed with a parallel combina-
tion of a 10μF capacitor and a 0.1μF ceramic chip capacitor.
The chip capacitors should be within 1/2 centimeter of the
power pins. Leadless chip capacitors are preferred because
they provide low lead inductance.
The converter’s digital logic supply (V
) should be well iso-
lated from the supply that is used for other digital circuitry on
the board. A common power supply should be used for both
V
(analog supply) and V
(digital supply), and each of these
supply pins should be separately bypassed with a 0.1μF ce-
ramic capacitor and a low ESR 10μF electrolytic capacitor. A
ferrite bead or inductor should be used between V
and V
D
to prevent noise coupling from the digital supply into the ana-
log circuit.
V
I/O is the power pin for the output driver. This pin may be
supplied with a potential between 3V and 5V. This makes it
easy to interface the ADC12081 with 3V or 5V logic families.
Powering the V
I/O from 3 Volts will also reduce power con-
sumption and noise generation due to output switching.
DO
NOT operate the V
I/O at a voltage higher than V
or V
!
All power supplies connected to the device should be ap-
plied simultaneously.
As is the case with all high speed converters, the ADC12081
is sensitive to power supply noise. Accordingly, the noise on
the analog supply pin should be minimized, keeping it below
100mV P-P.
A
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