參數(shù)資料
型號: ADC12081CIVT
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: ADC
英文描述: 12-Bit, 5 MHz Self-Calibrating, Pipelined A/D Converter
中文描述: 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32
封裝: LQFP-32
文件頁數(shù): 7/16頁
文件大小: 352K
代理商: ADC12081CIVT
AC Electrical Characteristics
(Continued)
Note 3:
When the input voltage at any pin exceeds the power supplies (that is, V
IN
<
AGND, or V
IN
>
V
A
, V
D
or V
D
I/O), the current at that pin should be limited
to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to
two.
Note 4:
The absolute maximum junction temperatures (T
max) for this device is 150C. The maximum allowable power consumption is dictated by T
max, the
junction-to-ambient thermal resistance (
θ
), and the ambient temperature, (T
), and can be calculated using the formula P
MAX = (T
max - T
)/
θ
. In the 32-pin
TQFP,
θ
is 74C/W, so P
MAX = 1,689 mW at 25C and 1,013 mW at the maximum operating ambient temperature of 75C. Note that the power consumption of
this device under normal operation will typically be about 125 mW (typical power consumption + 20 mW TTL output loading). The values for maximum power con-
sumption listed above will be reached only when the ADC12081 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power
supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5:
Human body model is 100 pF capacitor discharged through a 1.5k
resistor. Machine model is 220 pf discharged through ZERO Ohms.
Note 6:
See AN450,
Surface Mounting Methods and Their Effect on Product Reliability
, or the section entitled
Surface Mount
found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7:
The inputs are protected as shown below. Input voltage magnitudes up to 5V above V
A
or to 5V below GND will not damage this device, provided current
is limited per Note 3. However, errors in the A/D conversion can occur if the input goes above V
A
or below GND by more than 100 mV. As an example, if V
A
is 4.75V,
the full-scale input voltage must be
4.85V to ensure accurate conversions.
Note 8:
To guarantee accuracy, it is required that |V
A
- V
D
|
100mV and separate bypassed capacitors are used at each power supply pin.
Note 9:
With the test condition for V
REF
= +2.0V, the 12-bit LSB is 488μV.
Note 10:
Typical figures are at T
A
= T
J
= 25C, and represent most likely parametric norms.
Note 11:
Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12:
Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full-scall and
zero.
Note 13:
Timing specifications are tested at the TTL logic levels, V
IL
= 0.4V for a falling edge and V
IH
= 2.4V for a rising edge. TRI-STATE output voltage is forced
to 1.4V.
Note 14:
Optimum SNR performance will be obtained by keeping the reference input in the 1.8V to 2.2V range. The LM4041CIM3-ADJ (SOT-23 package), the
LM4041CIZ-ADJ (TO-92 package), or the LM4041CIM-ADJ (SOT-8 package) bandgap voltage reference is recommended for this application.
DS100150-8
A
www.national.com
7
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