參數(shù)資料
型號(hào)： ADC1210S065HN
廠商： NXP Semiconductors N.V.
元件分類(lèi)： 外設(shè)及接口
英文描述： Single 12-bit ADC 65 Msps CMOS or LVDS DDR digital outputs
封裝： ADC1210S065HN/C1<SOT618-1 (HVQFN40)|<<http://www.nxp.com/packages/SOT618-1.html<1<Always Pb-free,;ADC1210S065HN/C1<SOT618-1 (HVQFN40)|<<http://www.nxp.com/packages/SOT618
文件頁(yè)數(shù)： 16/39頁(yè)
文件大?。?/td> 283K
代理商： ADC1210S065HN
ADC1210S_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 23 December 2010
16 of 39
NXP Semiconductors
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
11.1.4
Selecting the output data format
The output data format can be selected via the SPI interface (offset binary, two’s
complement or gray code; see
Table 23
) or by using pin DFS in Pin control mode (offset
binary or two’s complement). Offset binary is selected when DFS is LOW. When DFS is
HIGH, two’s complement is selected.
11.2 Analog inputs
11.2.1
Input stage
The analog input of the ADC1210S supports a differential or a single-ended input drive.
Optimal performance is achieved using differential inputs with the common-mode input
voltage (V
I(cm)
) on pins INP and INM set to 0.5V
DDA
.
The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see
Section 11.3
and
Table 22
).
The equivalent circuit of the sample and hold input stage, including Electrostatic
Discharge (ESD) protection and circuit and package parasitics, is shown in
Figure 16
.
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
11.2.2
Anti-kickback circuitry
Anti-kickback circuitry (R-C filter in
Figure 17
) is needed to counteract the effects of a
charge injection generated by the sampling capacitance.
The RC filter is also used to filter noise from the signal before it reaches the sampling
stage. The value of the capacitor should be chosen to maximize noise attenuation without
degrading the settling time excessively.
Fig 16. Input sampling circuit
005aaa043
INP
Package
ESD
Parasitics
Switch
Ron = 15
Ω
4 pF
4 pF
Sampling
capacitor
Sampling
capacitor
Switch
Ron = 15
Ω
INM
8
7
Internal
clock
Internal
clock
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADC1210S065HN,518 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12bit 70dB 125MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADC1210S065HN/C1 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs
ADC1210S065HN/C1,5 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12bit 70dB 125MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADC1210S065HN-C1 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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