參數(shù)資料
型號: ADC12132CIMSA
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: ADC
英文描述: Switch-mode Lead-Acid Battery Charger with User-Selectable Charge Algorithms 16-SOIC -20 to 70
中文描述: 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝: SSOP-20
文件頁數(shù): 33/41頁
文件大?。?/td> 1085K
代理商: ADC12132CIMSA
Application Hints
(Continued)
TheADC12130/2/8 can be used in either ratiometric or abso-
lute reference applications. In ratiometric systems, the ana-
log input voltage is proportional to the voltage used for the
ADC’s reference voltage. When this voltage is the system
power supply, the V
REF+
pin is connected to V
A+
and V
REF
is connected to ground. This technique relaxes the system
reference stability requirements because the analog input
voltage and the ADC reference voltage move together. This
maintains the same output code for given input conditions.
For absolute accuracy, where the analog input voltage varies
between very specific voltage limits, a time and temperature
stable voltage source can be connected to the reference in-
puts. Typically, the reference voltage’s magnitude will require
an initial adjustment to null reference voltage induced
full-scale errors.
Below are recommended references along with some key
specifications.
Output
Voltage
Tolerance
±
0.5%
±
0.1%
Adjustable
Temperature
Coefficient
Part Number
LM4041CI-Adj
LM4040AI-4.1
Circuit of
Figure 16
The reference voltage inputs are not fully differential. The
ADC12130/2/8 will not generate correct conversions or com-
parisons if V
REF+
is taken below V
REF
. Correct conversions
result when V
REF+
and V
REF
differ by 1V and remain, at all
times, between ground and V
A+
. The V
REF
common mode
range, (V
REF+
+ V
REF
)/2 is restricted to (0.1 x V
A+
) to (0.6 x
V
A+
). Therefore, with V
A+
= 5V the center of the reference
ladder should not go below 0.5V or above 3.0V. Figure 17 is
a graphic representation of the voltage restrictions on V
REF+
and V
REF
.
±
100ppm/C
±
100ppm/C
±
2ppm/C
4.0 ANALOG INPUT VOLTAGE RANGE
The ADC12130/2/8’s fully differential ADC generate a two’s
complement output that is found by using the equation
shown below:
for (12-bit) resolution the Output Code =
Round off to the nearest integer value between 4096 to
4095 if the result of the above equation is not a whole num-
ber.
Examples are shown in the table below:
Digital
Output
Code
V
REF+
V
REF
V
IN+
V
IN
+2.5V
+4.096V
+4.096V
+4.096V
+1V
0V
0V
0V
+1.5V
+3V
+2.499V
0V
0V
0V
0,1111,1111,1111
0,1011,1011,1000
1,1111,1111,1111
1,0000,0000,0000
+2.500V
+4.096V
5.0 INPUT CURRENT
At the start of the acquisition window (t
) a charging current
flows into or out of the analog input pins (A/DIN1 and
A/DIN2) depending on the input voltage polarity. The analog
input pins are CH0–CH7 and COM when A/DIN1 is tied to
MUXOUT1 andA/DIN2 is tied to MUXOUT2. The peak value
of this input current will depend on the actual input voltage
applied, the source impedance and the internal multiplexer
switch on resistance. With MUXOUT1 tied to A/DIN1 and
MUXOUT2 tied to A/DIN2 the internal multiplexer switch on
resistance is typically 1.6 k
. The A/DIN1 and A/DIN2 mux
on resistance is typically 750
.
6.0 INPUT SOURCE RESISTANCE
For low impedance voltage sources (
<
600
), the input
charging current will decay, before the end of the S/H’s ac-
quisition time of 2 μs (10 CCLK periods with f
= 5 MHz), to
a value that will not introduce any conversion errors. For high
source impedances, the S/H’s acquisition time can be in-
DS012079-43
*
Tantalum
FIGURE 16. Low Drift Extremely
Stable Reference Circuit
DS012079-44
FIGURE 17. V
REF
Operating Range
A
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33
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