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參數(shù)資料
| 型號： | ADC12181EVAL |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 12-Bit, 5 MHz Self-Calibrating, Pipelined A/D Converter |
| 中文描述： | 12位，5兆赫自校準，流水線A / D轉換器 |
| 文件頁數(shù)： | 12/17頁 |
| 文件大?。?/td> | 322K |
| 代理商： | ADC12181EVAL |
Timing Diagrams
(Continued)
Functional Description
The ADC12181 is a monolithic CMOS analog-to-digital con-
verter capable of converting analog input signals into 12-bit
digital words at 10 megasamples per second (MSPS). This
device utilizes a proprietary pipeline architecture and algo-
rithm to minimize die size and power consumption. The
ADC12181 uses self-calibration and digital error correction
to maintain accuracy and performance over temperature.
The ADC12181 has an input sample-and-hold amplifier and
internal reference buffer. The analog input and the reference
voltage are converted to differential signals for internal use.
Using differential signals in the analog conversion core re-
duces crosstalk and noise pickup from the digital section and
power supply.
The pipeline conversion core has 15 sequential signal pro-
cessing stages. Each stage receives an analog signal from
the previous stage (called “residue” ) and produces a 1-bit
digital output that is sent to the digital correction module. At
each stage the analog signal received from the previous
stage is compared to an internally generated reference level.
It is then amplified by a factor of 2, and, depending on the
output of the comparator, the internal reference signal may
be subtracted from the amplifier output. This produces the
residue that is passed to the next stage.
The calibration module is activated at power-on or by user
request. During calibration the conversion core is put into a
special mode of operation in order to determine inherent
errors in the analog conversion blocks and to determine
correction coefficients for each digital output bit from the
conversion core and stores these coefficients in RAM. The
digital correction module uses the coefficients in RAM to
convert the raw data bits from the conversion core into the
12-bit digital output code.
Applications Information
1.0 ANALOG INPUTS
The ADC12181 has two single-ended analog inputs. V
REF
is
the reference input and V
IN
is the signal input.
1.1 Reference Input
The V
input must be driven from an accurate, stable
reference voltage source. of 1.8V to 2.2V, and bypassed to a
clean, quiet point in analog ground.
1.2 Analog Signal Input
The V
input must be driven with a low impedance signal
source that does not add any distortion to the input signal.
The ground reference for the V
input is the V
pin. The
V
pin must be connected to a clean, quiet point in
analog ground.
2.0 DIGITAL INPUTS
The ADC12181 has four digital inputs. They are CLOCK,
CAL, OE and PD.
2.1 CLOCK
The CLOCK signal drives an internal phase delay loop to
create timing for the ADC. The clock input should be driven
with a stable, low phase jitter TTL level clock signal in the
range of 1 to 10 MHz. The trace carrying the clock signal
should be as short as possible. This trace should not cross
any other signal line, analog or digital, not even at 90. A 100
Ohm resistor should be placed in series with the CLOCK pin,
as close to the pin as possible.
10103922
FIGURE 4. Reset and Calibration Timing
A
www.national.com
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